Unverified Commit 9ccbc2e1 authored by Pierre-Louis Bossart's avatar Pierre-Louis Bossart Committed by Mark Brown
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ASoC: SOF: Intel: hda: refine SSP count support 



The SSP count is incorrect for TGL and MTL devices, the SSP count is
limited to 3 (I2SPC parameter in the Integration HAS).

Signed-off-by: default avatarPierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
Reviewed-by: default avatarBard Liao <yung-chuan.liao@linux.intel.com>
Reviewed-by: default avatarPéter Ujfalusi <peter.ujfalusi@linux.intel.com>
Link: https://lore.kernel.org/r/20220919115350.43104-2-pierre-louis.bossart@linux.intel.com


Signed-off-by: default avatarMark Brown <broonie@kernel.org>
parent d3cfe45f

sound/soc/sof/intel/hda.h

+2 −0
Original line number Diff line number Diff line
@@ -435,6 +435,8 @@ 
#define APL_SSP_COUNT		6

#define CNL_SSP_COUNT		3

#define ICL_SSP_COUNT		6

#define TGL_SSP_COUNT		3

#define MTL_SSP_COUNT		3



/* SSP Registers */

#define SSP_SSC1_OFFSET		0x4

sound/soc/sof/intel/mtl.c

+1 −1
Original line number Diff line number Diff line
@@ -784,7 +784,7 @@ const struct sof_intel_dsp_desc mtl_chip_info = { 
	.ipc_ctl = MTL_DSP_REG_HFIPCXCTL,

	.rom_status_reg = MTL_DSP_ROM_STS,

	.rom_init_timeout	= 300,

	.ssp_count = ICL_SSP_COUNT,

	.ssp_count = MTL_SSP_COUNT,

	.ssp_base_offset = CNL_SSP_BASE_OFFSET,

	.sdw_shim_base = SDW_SHIM_BASE_ACE,

	.sdw_alh_base = SDW_ALH_BASE_ACE,

sound/soc/sof/intel/tgl.c

+4 −4
Original line number Diff line number Diff line
@@ -123,7 +123,7 @@ const struct sof_intel_dsp_desc tgl_chip_info = { 
	.ipc_ctl = CNL_DSP_REG_HIPCCTL,

	.rom_status_reg = HDA_DSP_SRAM_REG_ROM_STATUS,

	.rom_init_timeout	= 300,

	.ssp_count = ICL_SSP_COUNT,

	.ssp_count = TGL_SSP_COUNT,

	.ssp_base_offset = CNL_SSP_BASE_OFFSET,

	.sdw_shim_base = SDW_SHIM_BASE,

	.sdw_alh_base = SDW_ALH_BASE,
@@ -146,7 +146,7 @@ const struct sof_intel_dsp_desc tglh_chip_info = { 
	.ipc_ctl = CNL_DSP_REG_HIPCCTL,

	.rom_status_reg = HDA_DSP_SRAM_REG_ROM_STATUS,

	.rom_init_timeout	= 300,

	.ssp_count = ICL_SSP_COUNT,

	.ssp_count = TGL_SSP_COUNT,

	.ssp_base_offset = CNL_SSP_BASE_OFFSET,

	.sdw_shim_base = SDW_SHIM_BASE,

	.sdw_alh_base = SDW_ALH_BASE,
@@ -169,7 +169,7 @@ const struct sof_intel_dsp_desc ehl_chip_info = { 
	.ipc_ctl = CNL_DSP_REG_HIPCCTL,

	.rom_status_reg = HDA_DSP_SRAM_REG_ROM_STATUS,

	.rom_init_timeout	= 300,

	.ssp_count = ICL_SSP_COUNT,

	.ssp_count = TGL_SSP_COUNT,

	.ssp_base_offset = CNL_SSP_BASE_OFFSET,

	.sdw_shim_base = SDW_SHIM_BASE,

	.sdw_alh_base = SDW_ALH_BASE,
@@ -192,7 +192,7 @@ const struct sof_intel_dsp_desc adls_chip_info = { 
	.ipc_ctl = CNL_DSP_REG_HIPCCTL,

	.rom_status_reg = HDA_DSP_SRAM_REG_ROM_STATUS,

	.rom_init_timeout	= 300,

	.ssp_count = ICL_SSP_COUNT,

	.ssp_count = TGL_SSP_COUNT,

	.ssp_base_offset = CNL_SSP_BASE_OFFSET,

	.sdw_shim_base = SDW_SHIM_BASE,

	.sdw_alh_base = SDW_ALH_BASE,