Commit 9ca0674a authored by Likun Gao's avatar Likun Gao Committed by Alex Deucher
Browse files

drm/amdgpu: remove redundant logic related HDP 



Remove hdp_flush function from amdgpu_nbio struct as it have been unified
into hdp struct.
Remove the include about hdp register which was not used.
V2: Remove hdp golden setting which is unnecessary.

Signed-off-by: default avatarLikun Gao <Likun.Gao@amd.com>
Reviewed-by: default avatarHawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent bf087285

drivers/gpu/drm/amd/amdgpu/amdgpu_nbio.h

+0 −1
Original line number Diff line number Diff line
@@ -57,7 +57,6 @@ struct amdgpu_nbio_funcs { 
	u32 (*get_pcie_port_data_offset)(struct amdgpu_device *adev);

	u32 (*get_rev_id)(struct amdgpu_device *adev);

	void (*mc_access_enable)(struct amdgpu_device *adev, bool enable);

	void (*hdp_flush)(struct amdgpu_device *adev, struct amdgpu_ring *ring);

	u32 (*get_memsize)(struct amdgpu_device *adev);

	void (*sdma_doorbell_range)(struct amdgpu_device *adev, int instance,

			bool use_doorbell, int doorbell_index, int doorbell_size);

drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c

+0 −1
Original line number Diff line number Diff line
@@ -38,7 +38,6 @@ 
#include "gc/gc_9_0_sh_mask.h"



#include "vega10_enum.h"

#include "hdp/hdp_4_0_offset.h"



#include "soc15_common.h"

#include "clearstate_gfx9.h"

drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c

+0 −18
Original line number Diff line number Diff line
@@ -281,20 +281,6 @@ static const char *mmhub_client_ids_arcturus[][2] = { 
	[224+15][1] = "SDMA7",

};



static const u32 golden_settings_vega10_hdp[] =

{

	0xf64, 0x0fffffff, 0x00000000,

	0xf65, 0x0fffffff, 0x00000000,

	0xf66, 0x0fffffff, 0x00000000,

	0xf67, 0x0fffffff, 0x00000000,

	0xf68, 0x0fffffff, 0x00000000,

	0xf6a, 0x0fffffff, 0x00000000,

	0xf6b, 0x0fffffff, 0x00000000,

	0xf6c, 0x0fffffff, 0x00000000,

	0xf6d, 0x0fffffff, 0x00000000,

	0xf6e, 0x0fffffff, 0x00000000,

};



static const struct soc15_reg_golden golden_settings_mmhub_1_0_0[] =

{

	SOC15_REG_GOLDEN_VALUE(MMHUB, 0, mmDAGB1_WRCLI2, 0x00000007, 0xfe5fe0fa),
@@ -1580,10 +1566,6 @@ static int gmc_v9_0_hw_init(void *handle) 
		WREG32_FIELD15(DCE, 0, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0);

	}



	amdgpu_device_program_register_sequence(adev,

						golden_settings_vega10_hdp,

						ARRAY_SIZE(golden_settings_vega10_hdp));



	if (adev->mmhub.funcs->update_power_gating)

		adev->mmhub.funcs->update_power_gating(adev, true);

drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c

+0 −10
Original line number Diff line number Diff line
@@ -80,15 +80,6 @@ static void nbio_v2_3_mc_access_enable(struct amdgpu_device *adev, bool enable) 
		WREG32_SOC15(NBIO, 0, mmBIF_FB_EN, 0);

}



static void nbio_v2_3_hdp_flush(struct amdgpu_device *adev,

				struct amdgpu_ring *ring)

{

	if (!ring || !ring->funcs->emit_wreg)

		WREG32_NO_KIQ((adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >> 2, 0);

	else

		amdgpu_ring_emit_wreg(ring, (adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >> 2, 0);

}



static u32 nbio_v2_3_get_memsize(struct amdgpu_device *adev)

{

	return RREG32_SOC15(NBIO, 0, mmRCC_DEV0_EPF0_RCC_CONFIG_MEMSIZE);
@@ -366,7 +357,6 @@ const struct amdgpu_nbio_funcs nbio_v2_3_funcs = { 
	.get_pcie_data_offset = nbio_v2_3_get_pcie_data_offset,

	.get_rev_id = nbio_v2_3_get_rev_id,

	.mc_access_enable = nbio_v2_3_mc_access_enable,

	.hdp_flush = nbio_v2_3_hdp_flush,

	.get_memsize = nbio_v2_3_get_memsize,

	.sdma_doorbell_range = nbio_v2_3_sdma_doorbell_range,

	.vcn_doorbell_range = nbio_v2_3_vcn_doorbell_range,

drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c

+0 −13
Original line number Diff line number Diff line
@@ -59,18 +59,6 @@ static void nbio_v6_1_mc_access_enable(struct amdgpu_device *adev, bool enable) 
		WREG32_SOC15(NBIO, 0, mmBIF_FB_EN, 0);

}



static void nbio_v6_1_hdp_flush(struct amdgpu_device *adev,

				struct amdgpu_ring *ring)

{

	if (!ring || !ring->funcs->emit_wreg)

		WREG32_SOC15_NO_KIQ(NBIO, 0,

				    mmBIF_BX_PF0_HDP_MEM_COHERENCY_FLUSH_CNTL,

				    0);

	else

		amdgpu_ring_emit_wreg(ring, SOC15_REG_OFFSET(

			NBIO, 0, mmBIF_BX_PF0_HDP_MEM_COHERENCY_FLUSH_CNTL), 0);

}



static u32 nbio_v6_1_get_memsize(struct amdgpu_device *adev)

{

	return RREG32_SOC15(NBIO, 0, mmRCC_PF_0_0_RCC_CONFIG_MEMSIZE);
@@ -275,7 +263,6 @@ const struct amdgpu_nbio_funcs nbio_v6_1_funcs = { 
	.get_pcie_data_offset = nbio_v6_1_get_pcie_data_offset,

	.get_rev_id = nbio_v6_1_get_rev_id,

	.mc_access_enable = nbio_v6_1_mc_access_enable,

	.hdp_flush = nbio_v6_1_hdp_flush,

	.get_memsize = nbio_v6_1_get_memsize,

	.sdma_doorbell_range = nbio_v6_1_sdma_doorbell_range,

	.enable_doorbell_aperture = nbio_v6_1_enable_doorbell_aperture,