Commit 9ca05b0f authored by Maher Sanalla's avatar Maher Sanalla Committed by Leon Romanovsky
Browse files

RDMA/mlx5: Rely on RoCE fw cap instead of devlink when setting profile 



When the RDMA auxiliary driver probes, it sets its profile based on
devlink driverinit value. The latter might not be in sync with FW yet
(In case devlink reload is not performed), thus causing a mismatch
between RDMA driver and FW. This results in the following FW syndrome
when the RDMA driver tries to adjust RoCE state, which fails the probe:

"0xC1F678 | modify_nic_vport_context: roce_en set on a vport that
doesn't support roce"

To prevent this, select the PF profile based on FW RoCE capability
instead of relying on devlink driverinit value.
To provide backward compatibility of the RoCE disable feature, on older
FW's where roce_rw is not set (FW RoCE capability is read-only), keep
the current behavior e.g., rely on devlink driverinit value.

Fixes: fbfa97b4 ("net/mlx5: Disable roce at HCA level")
Reviewed-by: default avatarShay Drory <shayd@nvidia.com>
Reviewed-by: default avatarMichael Guralnik <michaelgur@nvidia.com>
Reviewed-by: default avatarSaeed Mahameed <saeedm@nvidia.com>
Signed-off-by: default avatarMaher Sanalla <msanalla@nvidia.com>
Link: https://lore.kernel.org/r/cb34ce9a1df4a24c135cb804db87f7d2418bd6cc.1661763459.git.leonro@nvidia.com


Signed-off-by: default avatarLeon Romanovsky <leon@kernel.org>
parent 85eaeb50

drivers/infiniband/hw/mlx5/main.c

+1 −1
Original line number Diff line number Diff line
@@ -4336,7 +4336,7 @@ static int mlx5r_probe(struct auxiliary_device *adev, 
	dev->mdev = mdev;

	dev->num_ports = num_ports;



	if (ll == IB_LINK_LAYER_ETHERNET && !mlx5_is_roce_init_enabled(mdev))

	if (ll == IB_LINK_LAYER_ETHERNET && !mlx5_get_roce_state(mdev))

		profile = &raw_eth_profile;

	else

		profile = &pf_profile;

drivers/net/ethernet/mellanox/mlx5/core/main.c

+21 −2
Original line number Diff line number Diff line
@@ -494,6 +494,24 @@ static int max_uc_list_get_devlink_param(struct mlx5_core_dev *dev) 
	return err;

}



bool mlx5_is_roce_on(struct mlx5_core_dev *dev)

{

	struct devlink *devlink = priv_to_devlink(dev);

	union devlink_param_value val;

	int err;



	err = devlink_param_driverinit_value_get(devlink,

						 DEVLINK_PARAM_GENERIC_ID_ENABLE_ROCE,

						 &val);



	if (!err)

		return val.vbool;



	mlx5_core_dbg(dev, "Failed to get param. err = %d\n", err);

	return MLX5_CAP_GEN(dev, roce);

}

EXPORT_SYMBOL(mlx5_is_roce_on);



static int handle_hca_cap_2(struct mlx5_core_dev *dev, void *set_ctx)

{

	void *set_hca_cap;
@@ -597,7 +615,8 @@ static int handle_hca_cap(struct mlx5_core_dev *dev, void *set_ctx) 
			 MLX5_CAP_GEN_MAX(dev, num_total_dynamic_vf_msix));



	if (MLX5_CAP_GEN(dev, roce_rw_supported))

		MLX5_SET(cmd_hca_cap, set_hca_cap, roce, mlx5_is_roce_init_enabled(dev));

		MLX5_SET(cmd_hca_cap, set_hca_cap, roce,

			 mlx5_is_roce_on(dev));



	max_uc_list = max_uc_list_get_devlink_param(dev);

	if (max_uc_list > 0)
@@ -623,7 +642,7 @@ static int handle_hca_cap(struct mlx5_core_dev *dev, void *set_ctx) 
 */

static bool is_roce_fw_disabled(struct mlx5_core_dev *dev)

{

	return (MLX5_CAP_GEN(dev, roce_rw_supported) && !mlx5_is_roce_init_enabled(dev)) ||

	return (MLX5_CAP_GEN(dev, roce_rw_supported) && !mlx5_is_roce_on(dev)) ||

		(!MLX5_CAP_GEN(dev, roce_rw_supported) && !MLX5_CAP_GEN(dev, roce));

}

include/linux/mlx5/driver.h

+10 −9
Original line number Diff line number Diff line
@@ -1279,16 +1279,17 @@ enum { 
	MLX5_TRIGGERED_CMD_COMP = (u64)1 << 32,

};



static inline bool mlx5_is_roce_init_enabled(struct mlx5_core_dev *dev)

bool mlx5_is_roce_on(struct mlx5_core_dev *dev);



static inline bool mlx5_get_roce_state(struct mlx5_core_dev *dev)

{

	struct devlink *devlink = priv_to_devlink(dev);

	union devlink_param_value val;

	int err;



	err = devlink_param_driverinit_value_get(devlink,

						 DEVLINK_PARAM_GENERIC_ID_ENABLE_ROCE,

						 &val);

	return err ? MLX5_CAP_GEN(dev, roce) : val.vbool;

	if (MLX5_CAP_GEN(dev, roce_rw_supported))

		return MLX5_CAP_GEN(dev, roce);



	/* If RoCE cap is read-only in FW, get RoCE state from devlink

	 * in order to support RoCE enable/disable feature

	 */

	return mlx5_is_roce_on(dev);

}



#endif /* MLX5_DRIVER_H */