Commit 9c8a47b4 authored by Rajan Vaja's avatar Rajan Vaja Committed by Michal Simek
Browse files

arm64: dts: xilinx: Add the clock nodes for zynqmp 



Add clock nodes for zynqmp based on CCF.

Signed-off-by: default avatarRajan Vaja <rajan.vaja@xilinx.com>
Signed-off-by: default avatarMichal Simek <michal.simek@xilinx.com>
parent df906cf5

arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi

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// SPDX-License-Identifier: GPL-2.0+

/*

 * Clock specification for Xilinx ZynqMP

 *

 * (C) Copyright 2017 - 2019, Xilinx, Inc.

 *

 * Michal Simek <michal.simek@xilinx.com>

 */



#include <dt-bindings/clock/xlnx-zynqmp-clk.h>

/ {

	pss_ref_clk: pss_ref_clk {

		u-boot,dm-pre-reloc;

		compatible = "fixed-clock";

		#clock-cells = <0>;

		clock-frequency = <33333333>;

	};



	video_clk: video_clk {

		u-boot,dm-pre-reloc;

		compatible = "fixed-clock";

		#clock-cells = <0>;

		clock-frequency = <27000000>;

	};



	pss_alt_ref_clk: pss_alt_ref_clk {

		u-boot,dm-pre-reloc;

		compatible = "fixed-clock";

		#clock-cells = <0>;

		clock-frequency = <0>;

	};



	gt_crx_ref_clk: gt_crx_ref_clk {

		u-boot,dm-pre-reloc;

		compatible = "fixed-clock";

		#clock-cells = <0>;

		clock-frequency = <108000000>;

	};



	aux_ref_clk: aux_ref_clk {

		u-boot,dm-pre-reloc;

		compatible = "fixed-clock";

		#clock-cells = <0>;

		clock-frequency = <27000000>;

	};

};



&can0 {

	clocks = <&zynqmp_clk CAN0_REF>, <&zynqmp_clk LPD_LSBUS>;

};



&can1 {

	clocks = <&zynqmp_clk CAN1_REF>, <&zynqmp_clk LPD_LSBUS>;

};



&cpu0 {

	clocks = <&zynqmp_clk ACPU>;

};



&fpd_dma_chan1 {

	clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;

};



&fpd_dma_chan2 {

	clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;

};



&fpd_dma_chan3 {

	clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;

};



&fpd_dma_chan4 {

	clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;

};



&fpd_dma_chan5 {

	clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;

};



&fpd_dma_chan6 {

	clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;

};



&fpd_dma_chan7 {

	clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;

};



&fpd_dma_chan8 {

	clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;

};



&lpd_dma_chan1 {

	clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;

};



&lpd_dma_chan2 {

	clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;

};



&lpd_dma_chan3 {

	clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;

};



&lpd_dma_chan4 {

	clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;

};



&lpd_dma_chan5 {

	clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;

};



&lpd_dma_chan6 {

	clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;

};



&lpd_dma_chan7 {

	clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;

};



&lpd_dma_chan8 {

	clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;

};



&gem0 {

	clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM0_REF>,

		 <&zynqmp_clk GEM0_TX>, <&zynqmp_clk GEM0_RX>,

		 <&zynqmp_clk GEM_TSU>;

	clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";

};



&gem1 {

	clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM1_REF>,

		 <&zynqmp_clk GEM1_TX>, <&zynqmp_clk GEM1_RX>,

		 <&zynqmp_clk GEM_TSU>;

	clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";

};



&gem2 {

	clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM2_REF>,

		 <&zynqmp_clk GEM2_TX>, <&zynqmp_clk GEM2_RX>,

		 <&zynqmp_clk GEM_TSU>;

	clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";

};



&gem3 {

	clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM3_REF>,

		 <&zynqmp_clk GEM3_TX>, <&zynqmp_clk GEM3_RX>,

		 <&zynqmp_clk GEM_TSU>;

	clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";

};



&gpio {

	clocks = <&zynqmp_clk LPD_LSBUS>;

};



&i2c0 {

	clocks = <&zynqmp_clk I2C0_REF>;

};



&i2c1 {

	clocks = <&zynqmp_clk I2C1_REF>;

};



&pcie {

	clocks = <&zynqmp_clk PCIE_REF>;

};



&sata {

	clocks = <&zynqmp_clk SATA_REF>;

};



&sdhci0 {

	clocks = <&zynqmp_clk SDIO0_REF>, <&zynqmp_clk LPD_LSBUS>;

};



&sdhci1 {

	clocks = <&zynqmp_clk SDIO1_REF>, <&zynqmp_clk LPD_LSBUS>;

};



&spi0 {

	clocks = <&zynqmp_clk SPI0_REF>, <&zynqmp_clk LPD_LSBUS>;

};



&spi1 {

	clocks = <&zynqmp_clk SPI1_REF>, <&zynqmp_clk LPD_LSBUS>;

};



&ttc0 {

	clocks = <&zynqmp_clk LPD_LSBUS>;

};



&ttc1 {

	clocks = <&zynqmp_clk LPD_LSBUS>;

};



&ttc2 {

	clocks = <&zynqmp_clk LPD_LSBUS>;

};



&ttc3 {

	clocks = <&zynqmp_clk LPD_LSBUS>;

};



&uart0 {

	clocks = <&zynqmp_clk UART0_REF>, <&zynqmp_clk LPD_LSBUS>;

};



&uart1 {

	clocks = <&zynqmp_clk UART1_REF>, <&zynqmp_clk LPD_LSBUS>;

};



&usb0 {

	clocks = <&zynqmp_clk USB0_BUS_REF>, <&zynqmp_clk USB3_DUAL_REF>;

};



&usb1 {

	clocks = <&zynqmp_clk USB1_BUS_REF>, <&zynqmp_clk USB3_DUAL_REF>;

};



&watchdog0 {

	clocks = <&zynqmp_clk WDT>;

};

arch/arm64/boot/dts/xilinx/zynqmp-zc1232-revA.dts

+2 −2
Original line number Diff line number Diff line
@@ -2,7 +2,7 @@ 
/*

 * dts file for Xilinx ZynqMP ZC1232

 *

 * (C) Copyright 2017 - 2018, Xilinx, Inc.

 * (C) Copyright 2017 - 2019, Xilinx, Inc.

 *

 * Michal Simek <michal.simek@xilinx.com>

 */
@@ -10,7 +10,7 @@ 
/dts-v1/;



#include "zynqmp.dtsi"

#include "zynqmp-clk.dtsi"

#include "zynqmp-clk-ccf.dtsi"



/ {

	model = "ZynqMP ZC1232 RevA";

arch/arm64/boot/dts/xilinx/zynqmp-zc1254-revA.dts

+2 −2
Original line number Diff line number Diff line
@@ -2,7 +2,7 @@ 
/*

 * dts file for Xilinx ZynqMP ZC1254

 *

 * (C) Copyright 2015 - 2018, Xilinx, Inc.

 * (C) Copyright 2015 - 2019, Xilinx, Inc.

 *

 * Michal Simek <michal.simek@xilinx.com>

 * Siva Durga Prasad Paladugu <sivadur@xilinx.com>
@@ -11,7 +11,7 @@ 
/dts-v1/;



#include "zynqmp.dtsi"

#include "zynqmp-clk.dtsi"

#include "zynqmp-clk-ccf.dtsi"



/ {

	model = "ZynqMP ZC1254 RevA";

arch/arm64/boot/dts/xilinx/zynqmp-zc1275-revA.dts

+2 −2
Original line number Diff line number Diff line
@@ -2,7 +2,7 @@ 
/*

 * dts file for Xilinx ZynqMP ZC1275

 *

 * (C) Copyright 2017 - 2018, Xilinx, Inc.

 * (C) Copyright 2017 - 2019, Xilinx, Inc.

 *

 * Michal Simek <michal.simek@xilinx.com>

 * Siva Durga Prasad Paladugu <sivadur@xilinx.com>
@@ -11,7 +11,7 @@ 
/dts-v1/;



#include "zynqmp.dtsi"

#include "zynqmp-clk.dtsi"

#include "zynqmp-clk-ccf.dtsi"



/ {

	model = "ZynqMP ZC1275 RevA";

arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm015-dc1.dts

+2 −2
Original line number Diff line number Diff line
@@ -2,7 +2,7 @@ 
/*

 * dts file for Xilinx ZynqMP zc1751-xm015-dc1

 *

 * (C) Copyright 2015 - 2018, Xilinx, Inc.

 * (C) Copyright 2015 - 2019, Xilinx, Inc.

 *

 * Michal Simek <michal.simek@xilinx.com>

 */
@@ -10,7 +10,7 @@ 
/dts-v1/;



#include "zynqmp.dtsi"

#include "zynqmp-clk.dtsi"

#include "zynqmp-clk-ccf.dtsi"

#include <dt-bindings/gpio/gpio.h>



/ {