Commit 9c7964b3 authored by Yonglong Liu's avatar Yonglong Liu Committed by Zheng Zengkai
Browse files

net: hns3: add support to utilize the firmware calculated shaping parameters 

mainline inclusion
from mainline-v5.11-rc1
commit e364ad30
category: feature
bugzilla: 173966
CVE: NA

Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=e364ad303fe3e96ff30fb05c031774ecbbce4af1



----------------------------------------------------------------------

Since the calculation of the driver is fixed, if the number of
queue or clock changed, the calculated result may be inaccurate.

So for compatible and maintainable, add a new flag to tell the
firmware to calculate the shaping parameters with the specified
rate.

Signed-off-by: default avatarYonglong Liu <liuyonglong@huawei.com>
Signed-off-by: default avatarHuazhong Tan <tanhuazhong@huawei.com>
Signed-off-by: default avatarJakub Kicinski <kuba@kernel.org>
Reviewed-by: default avatarli yongxin <liyongxin1@huawei.com>
Signed-off-by: default avatarZheng Zengkai <zhengzengkai@huawei.com>
parent 3161efe8

drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_tm.c

+31 −12
Original line number Diff line number Diff line
@@ -395,7 +395,7 @@ static u32 hclge_tm_get_shapping_para(u8 ir_b, u8 ir_u, u8 ir_s, 


static int hclge_tm_pg_shapping_cfg(struct hclge_dev *hdev,

				    enum hclge_shap_bucket bucket, u8 pg_id,

				    u32 shapping_para)

				    u32 shapping_para, u32 rate)

{

	struct hclge_pg_shapping_cmd *shap_cfg_cmd;

	enum hclge_opcode_type opcode;
@@ -411,6 +411,10 @@ static int hclge_tm_pg_shapping_cfg(struct hclge_dev *hdev, 


	shap_cfg_cmd->pg_shapping_para = cpu_to_le32(shapping_para);



	hnae3_set_bit(shap_cfg_cmd->flag, HCLGE_TM_RATE_VLD, 1);



	shap_cfg_cmd->pg_rate = cpu_to_le32(rate);



	return hclge_cmd_send(&hdev->hw, &desc, 1);

}
@@ -438,12 +442,16 @@ static int hclge_tm_port_shaper_cfg(struct hclge_dev *hdev) 


	shap_cfg_cmd->port_shapping_para = cpu_to_le32(shapping_para);



	hnae3_set_bit(shap_cfg_cmd->flag, HCLGE_TM_RATE_VLD, 1);



	shap_cfg_cmd->port_rate = cpu_to_le32(hdev->hw.mac.speed);



	return hclge_cmd_send(&hdev->hw, &desc, 1);

}



static int hclge_tm_pri_shapping_cfg(struct hclge_dev *hdev,

				     enum hclge_shap_bucket bucket, u8 pri_id,

				     u32 shapping_para)

				     u32 shapping_para, u32 rate)

{

	struct hclge_pri_shapping_cmd *shap_cfg_cmd;

	enum hclge_opcode_type opcode;
@@ -460,6 +468,10 @@ static int hclge_tm_pri_shapping_cfg(struct hclge_dev *hdev, 


	shap_cfg_cmd->pri_shapping_para = cpu_to_le32(shapping_para);



	hnae3_set_bit(shap_cfg_cmd->flag, HCLGE_TM_RATE_VLD, 1);



	shap_cfg_cmd->pri_rate = cpu_to_le32(rate);



	return hclge_cmd_send(&hdev->hw, &desc, 1);

}
@@ -561,6 +573,9 @@ int hclge_tm_qs_shaper_cfg(struct hclge_vport *vport, int max_tx_rate) 
		shap_cfg_cmd->qs_id = cpu_to_le16(vport->qs_offset + i);

		shap_cfg_cmd->qs_shapping_para = cpu_to_le32(shaper_para);



		hnae3_set_bit(shap_cfg_cmd->flag, HCLGE_TM_RATE_VLD, 1);

		shap_cfg_cmd->qs_rate = cpu_to_le32(max_tx_rate);



		ret = hclge_cmd_send(&hdev->hw, &desc, 1);

		if (ret) {

			dev_err(&hdev->pdev->dev,
@@ -762,9 +777,10 @@ static int hclge_tm_pg_shaper_cfg(struct hclge_dev *hdev) 


	/* Pg to pri */

	for (i = 0; i < hdev->tm_info.num_pg; i++) {

		u32 rate = hdev->tm_info.pg_info[i].bw_limit;



		/* Calc shaper para */

		ret = hclge_shaper_para_calc(hdev->tm_info.pg_info[i].bw_limit,

					     HCLGE_SHAPER_LVL_PG,

		ret = hclge_shaper_para_calc(rate, HCLGE_SHAPER_LVL_PG,

					     &ir_para, max_tm_rate);

		if (ret)

			return ret;
@@ -774,7 +790,7 @@ static int hclge_tm_pg_shaper_cfg(struct hclge_dev *hdev) 
							 HCLGE_SHAPER_BS_S_DEF);

		ret = hclge_tm_pg_shapping_cfg(hdev,

					       HCLGE_TM_SHAP_C_BUCKET, i,

					       shaper_para);

					       shaper_para, rate);

		if (ret)

			return ret;
@@ -785,7 +801,7 @@ static int hclge_tm_pg_shaper_cfg(struct hclge_dev *hdev) 
							 HCLGE_SHAPER_BS_S_DEF);

		ret = hclge_tm_pg_shapping_cfg(hdev,

					       HCLGE_TM_SHAP_P_BUCKET, i,

					       shaper_para);

					       shaper_para, rate);

		if (ret)

			return ret;

	}
@@ -891,8 +907,9 @@ static int hclge_tm_pri_tc_base_shaper_cfg(struct hclge_dev *hdev) 
	u32 i;



	for (i = 0; i < hdev->tm_info.num_tc; i++) {

		ret = hclge_shaper_para_calc(hdev->tm_info.tc_info[i].bw_limit,

					     HCLGE_SHAPER_LVL_PRI,

		u32 rate = hdev->tm_info.tc_info[i].bw_limit;



		ret = hclge_shaper_para_calc(rate, HCLGE_SHAPER_LVL_PRI,

					     &ir_para, max_tm_rate);

		if (ret)

			return ret;
@@ -901,7 +918,7 @@ static int hclge_tm_pri_tc_base_shaper_cfg(struct hclge_dev *hdev) 
							 HCLGE_SHAPER_BS_U_DEF,

							 HCLGE_SHAPER_BS_S_DEF);

		ret = hclge_tm_pri_shapping_cfg(hdev, HCLGE_TM_SHAP_C_BUCKET, i,

						shaper_para);

						shaper_para, rate);

		if (ret)

			return ret;
@@ -911,7 +928,7 @@ static int hclge_tm_pri_tc_base_shaper_cfg(struct hclge_dev *hdev) 
							 HCLGE_SHAPER_BS_U_DEF,

							 HCLGE_SHAPER_BS_S_DEF);

		ret = hclge_tm_pri_shapping_cfg(hdev, HCLGE_TM_SHAP_P_BUCKET, i,

						shaper_para);

						shaper_para, rate);

		if (ret)

			return ret;

	}
@@ -936,7 +953,8 @@ static int hclge_tm_pri_vnet_base_shaper_pri_cfg(struct hclge_vport *vport) 
						 HCLGE_SHAPER_BS_U_DEF,

						 HCLGE_SHAPER_BS_S_DEF);

	ret = hclge_tm_pri_shapping_cfg(hdev, HCLGE_TM_SHAP_C_BUCKET,

					vport->vport_id, shaper_para);

					vport->vport_id, shaper_para,

					vport->bw_limit);

	if (ret)

		return ret;
@@ -945,7 +963,8 @@ static int hclge_tm_pri_vnet_base_shaper_pri_cfg(struct hclge_vport *vport) 
						 HCLGE_SHAPER_BS_U_DEF,

						 HCLGE_SHAPER_BS_S_DEF);

	ret = hclge_tm_pri_shapping_cfg(hdev, HCLGE_TM_SHAP_P_BUCKET,

					vport->vport_id, shaper_para);

					vport->vport_id, shaper_para,

					vport->bw_limit);

	if (ret)

		return ret;

drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_tm.h

+15 −0
Original line number Diff line number Diff line
@@ -92,22 +92,34 @@ enum hclge_shap_bucket { 
	HCLGE_TM_SHAP_P_BUCKET,

};



/* set bit HCLGE_TM_RATE_VLD to 1 means use 'rate' to config shaping */

#define HCLGE_TM_RATE_VLD	0



struct hclge_pri_shapping_cmd {

	u8 pri_id;

	u8 rsvd[3];

	__le32 pri_shapping_para;

	u8 flag;

	u8 rsvd1[3];

	__le32 pri_rate;

};



struct hclge_pg_shapping_cmd {

	u8 pg_id;

	u8 rsvd[3];

	__le32 pg_shapping_para;

	u8 flag;

	u8 rsvd1[3];

	__le32 pg_rate;

};



struct hclge_qs_shapping_cmd {

	__le16 qs_id;

	u8 rsvd[2];

	__le32 qs_shapping_para;

	u8 flag;

	u8 rsvd1[3];

	__le32 qs_rate;

};



#define HCLGE_BP_GRP_NUM		32
@@ -150,6 +162,9 @@ struct hclge_pfc_stats_cmd { 


struct hclge_port_shapping_cmd {

	__le32 port_shapping_para;

	u8 flag;

	u8 rsvd[3];

	__le32 port_rate;

};



struct hclge_shaper_ir_para {