Commit 9c674947 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'clk-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux 

Pull clk fixes from Stephen Boyd:
 "One more small batch of clk driver fixes:

   - A fix for the Qualcomm GDSC power domain delays that avoids black
     screens at boot on some more recent SoCs that use a different delay
     than the hard-coded delays in the driver.

   - A build fix LAN966X clk driver that let it be built on
     architectures that didn't have IOMEM"

* tag 'clk-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux:
  clk: lan966x: Fix linking error
  clk: qcom: dispcc: Update the transition delay for MDSS GDSC
  clk: qcom: gdsc: Add support to update GDSC transition delay
parents b5521fe9 aa091a6a

drivers/clk/Kconfig

+2 −0
Original line number Diff line number Diff line
@@ -231,6 +231,8 @@ config COMMON_CLK_GEMINI 


config COMMON_CLK_LAN966X

	bool "Generic Clock Controller driver for LAN966X SoC"

	depends on HAS_IOMEM

	depends on OF

	help

	  This driver provides support for Generic Clock Controller(GCK) on

	  LAN966X SoC. GCK generates and supplies clock to various peripherals

drivers/clk/qcom/dispcc-sc7180.c

+4 −1
Original line number Diff line number Diff line 
// SPDX-License-Identifier: GPL-2.0-only

/*

 * Copyright (c) 2019, The Linux Foundation. All rights reserved.

 * Copyright (c) 2019, 2022, The Linux Foundation. All rights reserved.

 */



#include <linux/clk-provider.h>
@@ -625,6 +625,9 @@ static struct clk_branch disp_cc_mdss_vsync_clk = { 


static struct gdsc mdss_gdsc = {

	.gdscr = 0x3000,

	.en_rest_wait_val = 0x2,

	.en_few_wait_val = 0x2,

	.clk_dis_wait_val = 0xf,

	.pd = {

		.name = "mdss_gdsc",

	},

drivers/clk/qcom/dispcc-sc7280.c

+4 −1
Original line number Diff line number Diff line 
// SPDX-License-Identifier: GPL-2.0-only

/*

 * Copyright (c) 2021, The Linux Foundation. All rights reserved.

 * Copyright (c) 2021-2022, The Linux Foundation. All rights reserved.

 */



#include <linux/clk-provider.h>
@@ -787,6 +787,9 @@ static struct clk_branch disp_cc_sleep_clk = { 


static struct gdsc disp_cc_mdss_core_gdsc = {

	.gdscr = 0x1004,

	.en_rest_wait_val = 0x2,

	.en_few_wait_val = 0x2,

	.clk_dis_wait_val = 0xf,

	.pd = {

		.name = "disp_cc_mdss_core_gdsc",

	},

drivers/clk/qcom/dispcc-sm8250.c

+4 −1
Original line number Diff line number Diff line 
// SPDX-License-Identifier: GPL-2.0

/*

 * Copyright (c) 2018-2020, The Linux Foundation. All rights reserved.

 * Copyright (c) 2018-2020, 2022, The Linux Foundation. All rights reserved.

 */



#include <linux/clk-provider.h>
@@ -1126,6 +1126,9 @@ static struct clk_branch disp_cc_mdss_vsync_clk = { 


static struct gdsc mdss_gdsc = {

	.gdscr = 0x3000,

	.en_rest_wait_val = 0x2,

	.en_few_wait_val = 0x2,

	.clk_dis_wait_val = 0xf,

	.pd = {

		.name = "mdss_gdsc",

	},

drivers/clk/qcom/gdsc.c

+21 −5
Original line number Diff line number Diff line 
// SPDX-License-Identifier: GPL-2.0-only

/*

 * Copyright (c) 2015, 2017-2018, The Linux Foundation. All rights reserved.

 * Copyright (c) 2015, 2017-2018, 2022, The Linux Foundation. All rights reserved.

 */



#include <linux/bitops.h>
@@ -35,9 +35,14 @@ 
#define CFG_GDSCR_OFFSET		0x4



/* Wait 2^n CXO cycles between all states. Here, n=2 (4 cycles). */

#define EN_REST_WAIT_VAL	(0x2 << 20)

#define EN_FEW_WAIT_VAL		(0x8 << 16)

#define CLK_DIS_WAIT_VAL	(0x2 << 12)

#define EN_REST_WAIT_VAL	0x2

#define EN_FEW_WAIT_VAL		0x8

#define CLK_DIS_WAIT_VAL	0x2



/* Transition delay shifts */

#define EN_REST_WAIT_SHIFT	20

#define EN_FEW_WAIT_SHIFT	16

#define CLK_DIS_WAIT_SHIFT	12



#define RETAIN_MEM		BIT(14)

#define RETAIN_PERIPH		BIT(13)
@@ -380,7 +385,18 @@ static int gdsc_init(struct gdsc *sc) 
	 */

	mask = HW_CONTROL_MASK | SW_OVERRIDE_MASK |

	       EN_REST_WAIT_MASK | EN_FEW_WAIT_MASK | CLK_DIS_WAIT_MASK;

	val = EN_REST_WAIT_VAL | EN_FEW_WAIT_VAL | CLK_DIS_WAIT_VAL;



	if (!sc->en_rest_wait_val)

		sc->en_rest_wait_val = EN_REST_WAIT_VAL;

	if (!sc->en_few_wait_val)

		sc->en_few_wait_val = EN_FEW_WAIT_VAL;

	if (!sc->clk_dis_wait_val)

		sc->clk_dis_wait_val = CLK_DIS_WAIT_VAL;



	val = sc->en_rest_wait_val << EN_REST_WAIT_SHIFT |

		sc->en_few_wait_val << EN_FEW_WAIT_SHIFT |

		sc->clk_dis_wait_val << CLK_DIS_WAIT_SHIFT;



	ret = regmap_update_bits(sc->regmap, sc->gdscr, mask, val);

	if (ret)

		return ret;