Loading drivers/char/agp/intel-gtt.c +5 −4 Original line number Diff line number Diff line Loading @@ -75,6 +75,7 @@ static struct _intel_private { struct resource ifp_resource; int resource_valid; struct page *scratch_page; phys_addr_t scratch_page_dma; int refcount; } intel_private; Loading Loading @@ -297,9 +298,9 @@ static int intel_gtt_setup_scratch_page(void) if (pci_dma_mapping_error(intel_private.pcidev, dma_addr)) return -EINVAL; intel_private.base.scratch_page_dma = dma_addr; intel_private.scratch_page_dma = dma_addr; } else intel_private.base.scratch_page_dma = page_to_phys(page); intel_private.scratch_page_dma = page_to_phys(page); intel_private.scratch_page = page; Loading Loading @@ -546,7 +547,7 @@ static unsigned int intel_gtt_mappable_entries(void) static void intel_gtt_teardown_scratch_page(void) { set_pages_wb(intel_private.scratch_page, 1); pci_unmap_page(intel_private.pcidev, intel_private.base.scratch_page_dma, pci_unmap_page(intel_private.pcidev, intel_private.scratch_page_dma, PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); put_page(intel_private.scratch_page); __free_page(intel_private.scratch_page); Loading Loading @@ -891,7 +892,7 @@ void intel_gtt_clear_range(unsigned int first_entry, unsigned int num_entries) unsigned int i; for (i = first_entry; i < (first_entry + num_entries); i++) { intel_private.driver->write_entry(intel_private.base.scratch_page_dma, intel_private.driver->write_entry(intel_private.scratch_page_dma, i, 0); } readl(intel_private.gtt+i-1); Loading drivers/gpu/drm/i915/i915_drv.h +2 −0 Original line number Diff line number Diff line Loading @@ -383,6 +383,8 @@ struct i915_gtt { void __iomem *gsm; bool do_idle_maps; dma_addr_t scratch_page_dma; struct page *scratch_page; }; #define I915_PPGTT_PD_ENTRIES 512 Loading drivers/gpu/drm/i915/i915_gem_gtt.c +8 −8 Original line number Diff line number Diff line Loading @@ -162,7 +162,7 @@ int i915_gem_init_aliasing_ppgtt(struct drm_device *dev) } } ppgtt->scratch_page_dma_addr = dev_priv->mm.gtt->scratch_page_dma; ppgtt->scratch_page_dma_addr = dev_priv->gtt.scratch_page_dma; i915_ppgtt_clear_range(ppgtt, 0, ppgtt->num_pd_entries*I915_PPGTT_PT_ENTRIES); Loading Loading @@ -396,7 +396,7 @@ static void i915_ggtt_clear_range(struct drm_device *dev, first_entry, num_entries, max_entries)) num_entries = max_entries; scratch_pte = pte_encode(dev, dev_priv->mm.gtt->scratch_page_dma, I915_CACHE_LLC); scratch_pte = pte_encode(dev, dev_priv->gtt.scratch_page_dma, I915_CACHE_LLC); for (i = 0; i < num_entries; i++) iowrite32(scratch_pte, >t_base[i]); readl(gtt_base); Loading Loading @@ -659,8 +659,8 @@ static int setup_scratch_page(struct drm_device *dev) #else dma_addr = page_to_phys(page); #endif dev_priv->mm.gtt->scratch_page = page; dev_priv->mm.gtt->scratch_page_dma = dma_addr; dev_priv->gtt.scratch_page = page; dev_priv->gtt.scratch_page_dma = dma_addr; return 0; } Loading @@ -668,11 +668,11 @@ static int setup_scratch_page(struct drm_device *dev) static void teardown_scratch_page(struct drm_device *dev) { struct drm_i915_private *dev_priv = dev->dev_private; set_pages_wb(dev_priv->mm.gtt->scratch_page, 1); pci_unmap_page(dev->pdev, dev_priv->mm.gtt->scratch_page_dma, set_pages_wb(dev_priv->gtt.scratch_page, 1); pci_unmap_page(dev->pdev, dev_priv->gtt.scratch_page_dma, PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); put_page(dev_priv->mm.gtt->scratch_page); __free_page(dev_priv->mm.gtt->scratch_page); put_page(dev_priv->gtt.scratch_page); __free_page(dev_priv->gtt.scratch_page); } static inline unsigned int gen6_get_total_gtt_size(u16 snb_gmch_ctl) Loading include/drm/intel-gtt.h +0 −3 Original line number Diff line number Diff line Loading @@ -13,9 +13,6 @@ struct intel_gtt { unsigned int gtt_mappable_entries; /* Whether i915 needs to use the dmar apis or not. */ unsigned int needs_dmar : 1; /* Share the scratch page dma with ppgtts. */ dma_addr_t scratch_page_dma; struct page *scratch_page; /* needed for ioremap in drm/i915 */ phys_addr_t gma_bus_addr; } *intel_gtt_get(void); Loading Loading
drivers/char/agp/intel-gtt.c +5 −4 Original line number Diff line number Diff line Loading @@ -75,6 +75,7 @@ static struct _intel_private { struct resource ifp_resource; int resource_valid; struct page *scratch_page; phys_addr_t scratch_page_dma; int refcount; } intel_private; Loading Loading @@ -297,9 +298,9 @@ static int intel_gtt_setup_scratch_page(void) if (pci_dma_mapping_error(intel_private.pcidev, dma_addr)) return -EINVAL; intel_private.base.scratch_page_dma = dma_addr; intel_private.scratch_page_dma = dma_addr; } else intel_private.base.scratch_page_dma = page_to_phys(page); intel_private.scratch_page_dma = page_to_phys(page); intel_private.scratch_page = page; Loading Loading @@ -546,7 +547,7 @@ static unsigned int intel_gtt_mappable_entries(void) static void intel_gtt_teardown_scratch_page(void) { set_pages_wb(intel_private.scratch_page, 1); pci_unmap_page(intel_private.pcidev, intel_private.base.scratch_page_dma, pci_unmap_page(intel_private.pcidev, intel_private.scratch_page_dma, PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); put_page(intel_private.scratch_page); __free_page(intel_private.scratch_page); Loading Loading @@ -891,7 +892,7 @@ void intel_gtt_clear_range(unsigned int first_entry, unsigned int num_entries) unsigned int i; for (i = first_entry; i < (first_entry + num_entries); i++) { intel_private.driver->write_entry(intel_private.base.scratch_page_dma, intel_private.driver->write_entry(intel_private.scratch_page_dma, i, 0); } readl(intel_private.gtt+i-1); Loading
drivers/gpu/drm/i915/i915_drv.h +2 −0 Original line number Diff line number Diff line Loading @@ -383,6 +383,8 @@ struct i915_gtt { void __iomem *gsm; bool do_idle_maps; dma_addr_t scratch_page_dma; struct page *scratch_page; }; #define I915_PPGTT_PD_ENTRIES 512 Loading
drivers/gpu/drm/i915/i915_gem_gtt.c +8 −8 Original line number Diff line number Diff line Loading @@ -162,7 +162,7 @@ int i915_gem_init_aliasing_ppgtt(struct drm_device *dev) } } ppgtt->scratch_page_dma_addr = dev_priv->mm.gtt->scratch_page_dma; ppgtt->scratch_page_dma_addr = dev_priv->gtt.scratch_page_dma; i915_ppgtt_clear_range(ppgtt, 0, ppgtt->num_pd_entries*I915_PPGTT_PT_ENTRIES); Loading Loading @@ -396,7 +396,7 @@ static void i915_ggtt_clear_range(struct drm_device *dev, first_entry, num_entries, max_entries)) num_entries = max_entries; scratch_pte = pte_encode(dev, dev_priv->mm.gtt->scratch_page_dma, I915_CACHE_LLC); scratch_pte = pte_encode(dev, dev_priv->gtt.scratch_page_dma, I915_CACHE_LLC); for (i = 0; i < num_entries; i++) iowrite32(scratch_pte, >t_base[i]); readl(gtt_base); Loading Loading @@ -659,8 +659,8 @@ static int setup_scratch_page(struct drm_device *dev) #else dma_addr = page_to_phys(page); #endif dev_priv->mm.gtt->scratch_page = page; dev_priv->mm.gtt->scratch_page_dma = dma_addr; dev_priv->gtt.scratch_page = page; dev_priv->gtt.scratch_page_dma = dma_addr; return 0; } Loading @@ -668,11 +668,11 @@ static int setup_scratch_page(struct drm_device *dev) static void teardown_scratch_page(struct drm_device *dev) { struct drm_i915_private *dev_priv = dev->dev_private; set_pages_wb(dev_priv->mm.gtt->scratch_page, 1); pci_unmap_page(dev->pdev, dev_priv->mm.gtt->scratch_page_dma, set_pages_wb(dev_priv->gtt.scratch_page, 1); pci_unmap_page(dev->pdev, dev_priv->gtt.scratch_page_dma, PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); put_page(dev_priv->mm.gtt->scratch_page); __free_page(dev_priv->mm.gtt->scratch_page); put_page(dev_priv->gtt.scratch_page); __free_page(dev_priv->gtt.scratch_page); } static inline unsigned int gen6_get_total_gtt_size(u16 snb_gmch_ctl) Loading
include/drm/intel-gtt.h +0 −3 Original line number Diff line number Diff line Loading @@ -13,9 +13,6 @@ struct intel_gtt { unsigned int gtt_mappable_entries; /* Whether i915 needs to use the dmar apis or not. */ unsigned int needs_dmar : 1; /* Share the scratch page dma with ppgtts. */ dma_addr_t scratch_page_dma; struct page *scratch_page; /* needed for ioremap in drm/i915 */ phys_addr_t gma_bus_addr; } *intel_gtt_get(void); Loading