Commit 9c37b09d authored by Linus Walleij's avatar Linus Walleij Committed by David S. Miller
Browse files

dt-bindings: net: Add bindings for IXP4xx V.35 WAN HSS 



This adds device tree bindings for the IXP4xx V.35 WAN high
speed serial (HSS) link.

An example is added to the NPE example where the HSS appears
as a child.

Cc: devicetree@vger.kernel.org
Signed-off-by: default avatarLinus Walleij <linus.walleij@linaro.org>
Reviewed-by: default avatarRob Herring <robh@kernel.org>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent ef136837

Documentation/devicetree/bindings/firmware/intel,ixp4xx-network-processing-engine.yaml

+35 −0
Original line number Diff line number Diff line
@@ -37,6 +37,20 @@ properties: 
      should be named with the instance number of the NPE engine used for

      the crypto engine.



  "#address-cells":

    const: 1



  "#size-cells":

    const: 0



patternProperties:

  hss@[0-9]+$:

    $ref: /schemas/net/intel,ixp4xx-hss.yaml#

    type: object

    description: Optional node for the High Speed Serial link (HSS), the

      node should be named with the instance number of the NPE engine

      used for the HSS.



required:

  - compatible

  - reg
@@ -45,9 +59,30 @@ additionalProperties: false 


examples:

  - |

    #include <dt-bindings/gpio/gpio.h>



    npe: npe@c8006000 {

         compatible = "intel,ixp4xx-network-processing-engine";

         reg = <0xc8006000 0x1000>, <0xc8007000 0x1000>, <0xc8008000 0x1000>;

         #address-cells = <1>;

         #size-cells = <0>;



         hss@0 {

             compatible = "intel,ixp4xx-hss";

             reg = <0>;

             intel,npe-handle = <&npe 0>;

             intel,queue-chl-rxtrig = <&qmgr 12>;

             intel,queue-chl-txready = <&qmgr 34>;

             intel,queue-pkt-rx = <&qmgr 13>;

             intel,queue-pkt-tx = <&qmgr 14>, <&qmgr 15>, <&qmgr 16>, <&qmgr 17>;

             intel,queue-pkt-rxfree = <&qmgr 18>, <&qmgr 19>, <&qmgr 20>, <&qmgr 21>;

             intel,queue-pkt-txdone = <&qmgr 22>;

             cts-gpios = <&gpio0 10 GPIO_ACTIVE_LOW>;

             rts-gpios = <&gpio0 14 GPIO_ACTIVE_LOW>;

             dcd-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>;

             dtr-gpios = <&gpio_74 2 GPIO_ACTIVE_LOW>;

             clk-internal-gpios = <&gpio_74 0 GPIO_ACTIVE_HIGH>;

         };



         crypto {

             compatible = "intel,ixp4xx-crypto";

Documentation/devicetree/bindings/net/intel,ixp4xx-hss.yaml

0 → 100644
+100 −0
Original line number Diff line number Diff line 
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)

# Copyright 2021 Linaro Ltd.

%YAML 1.2

---

$id: "http://devicetree.org/schemas/net/intel,ixp4xx-hss.yaml#"

$schema: "http://devicetree.org/meta-schemas/core.yaml#"



title: Intel IXP4xx V.35 WAN High Speed Serial Link (HSS)



maintainers:

  - Linus Walleij <linus.walleij@linaro.org>



description: |

  The Intel IXP4xx HSS makes use of the IXP4xx NPE (Network

  Processing Engine) and the IXP4xx Queue Manager to process

  V.35 Wideband Modem (WAN) links.



properties:

  compatible:

    const: intel,ixp4xx-hss



  reg:

    maxItems: 1

    description: The HSS instance



  intel,npe-handle:

    $ref: '/schemas/types.yaml#/definitions/phandle-array'

    maxItems: 1

    description: phandle to the NPE this HSS instance is using

      and the instance to use in the second cell



  intel,queue-chl-rxtrig:

    $ref: '/schemas/types.yaml#/definitions/phandle-array'

    maxItems: 1

    description: phandle to the RX trigger queue on the NPE



  intel,queue-chl-txready:

    $ref: '/schemas/types.yaml#/definitions/phandle-array'

    maxItems: 1

    description: phandle to the TX ready queue on the NPE



  intel,queue-pkt-rx:

    $ref: '/schemas/types.yaml#/definitions/phandle-array'

    maxItems: 1

    description: phandle to the packet RX queue on the NPE



  intel,queue-pkt-tx:

    $ref: '/schemas/types.yaml#/definitions/phandle-array'

    maxItems: 4

    description: phandle to the packet TX0, TX1, TX2 and TX3 queues on the NPE



  intel,queue-pkt-rxfree:

    $ref: '/schemas/types.yaml#/definitions/phandle-array'

    maxItems: 4

    description: phandle to the packet RXFREE0, RXFREE1, RXFREE2 and

      RXFREE3 queues on the NPE



  intel,queue-pkt-txdone:

    $ref: '/schemas/types.yaml#/definitions/phandle-array'

    maxItems: 1

    description: phandle to the packet TXDONE queue on the NPE



  cts-gpios:

    maxItems: 1

    description: Clear To Send (CTS) GPIO line



  rts-gpios:

    maxItems: 1

    description: Ready To Send (RTS) GPIO line



  dcd-gpios:

    maxItems: 1

    description: Data Carrier Detect (DCD) GPIO line



  dtr-gpios:

    maxItems: 1

    description: Data Terminal Ready (DTR) GPIO line



  clk-internal-gpios:

    maxItems: 1

    description: Clock internal GPIO line, driving this high will make the HSS

      use internal clocking as opposed to external clocking



required:

  - compatible

  - reg

  - intel,npe-handle

  - intel,queue-chl-rxtrig

  - intel,queue-chl-txready

  - intel,queue-pkt-rx

  - intel,queue-pkt-tx

  - intel,queue-pkt-rxfree

  - intel,queue-pkt-txdone

  - cts-gpios

  - rts-gpios

  - dcd-gpios

  - dtr-gpios

  - clk-internal-gpios



additionalProperties: false