Commit 9c0cef23 authored by Jack Xu's avatar Jack Xu Committed by Herbert Xu
Browse files

crypto: qat - add gen4 firmware loader 



Add support for the QAT gen4 devices in the firmware loader.

Signed-off-by: default avatarJack Xu <jack.xu@intel.com>
Reviewed-by: default avatarGiovanni Cabiddu <giovanni.cabiddu@intel.com>
Signed-off-by: default avatarHerbert Xu <herbert@gondor.apana.org.au>
parent 2778d64c

drivers/crypto/qat/qat_common/adf_accel_devices.h

+2 −0
Original line number Diff line number Diff line
@@ -15,6 +15,8 @@ 
#define ADF_C62XVF_DEVICE_NAME "c6xxvf"

#define ADF_C3XXX_DEVICE_NAME "c3xxx"

#define ADF_C3XXXVF_DEVICE_NAME "c3xxxvf"

#define ADF_4XXX_PCI_DEVICE_ID 0x4940

#define ADF_4XXXIOV_PCI_DEVICE_ID 0x4941

#define ADF_ERRSOU3 (0x3A000 + 0x0C)

#define ADF_ERRSOU5 (0x3A000 + 0xD8)

#define ADF_DEVICE_FUSECTL_OFFSET 0x40

drivers/crypto/qat/qat_common/icp_qat_hal.h

+11 −1
Original line number Diff line number Diff line
@@ -10,6 +10,14 @@ enum hal_global_csr { 
	ICP_GLOBAL_CLK_ENABLE = 0xA50

};



enum {

	MISC_CONTROL_C4XXX = 0xAA0,

	ICP_RESET_CPP0 = 0x938,

	ICP_RESET_CPP1 = 0x93c,

	ICP_GLOBAL_CLK_ENABLE_CPP0 = 0x964,

	ICP_GLOBAL_CLK_ENABLE_CPP1 = 0x968

};



enum hal_ae_csr {

	USTORE_ADDRESS = 0x000,

	USTORE_DATA_LOWER = 0x004,
@@ -111,7 +119,9 @@ enum fcu_sts { 
#define ICP_QAT_CAP_OFFSET (ICP_QAT_AE_OFFSET + 0x10000)

#define LOCAL_TO_XFER_REG_OFFSET 0x800

#define ICP_QAT_EP_OFFSET 0x3a000



#define ICP_QAT_EP_OFFSET_4XXX   0x200000 /* HI MMIO CSRs */

#define ICP_QAT_AE_OFFSET_4XXX   0x600000

#define ICP_QAT_CAP_OFFSET_4XXX  0x640000

#define SET_CAP_CSR(handle, csr, val) \

	ADF_CSR_WR((handle)->hal_cap_g_ctl_csr_addr_v, csr, val)

#define GET_CAP_CSR(handle, csr) \

drivers/crypto/qat/qat_common/icp_qat_uclo.h

+2 −0
Original line number Diff line number Diff line
@@ -6,6 +6,7 @@ 
#define ICP_QAT_AC_895XCC_DEV_TYPE 0x00400000

#define ICP_QAT_AC_C62X_DEV_TYPE   0x01000000

#define ICP_QAT_AC_C3XXX_DEV_TYPE  0x02000000

#define ICP_QAT_AC_4XXX_A_DEV_TYPE 0x08000000

#define ICP_QAT_UCLO_MAX_AE       12

#define ICP_QAT_UCLO_MAX_CTX      8

#define ICP_QAT_UCLO_MAX_UIMAGE   (ICP_QAT_UCLO_MAX_AE * ICP_QAT_UCLO_MAX_CTX)
@@ -13,6 +14,7 @@ 
#define ICP_QAT_UCLO_MAX_XFER_REG 128

#define ICP_QAT_UCLO_MAX_GPR_REG  128

#define ICP_QAT_UCLO_MAX_LMEM_REG 1024

#define ICP_QAT_UCLO_MAX_LMEM_REG_2X 1280

#define ICP_QAT_UCLO_AE_ALL_CTX   0xff

#define ICP_QAT_UOF_OBJID_LEN     8

#define ICP_QAT_UOF_FID 0xc6c2

drivers/crypto/qat/qat_common/qat_hal.c

+61 −16
Original line number Diff line number Diff line
@@ -695,6 +695,39 @@ static int qat_hal_chip_init(struct icp_qat_fw_loader_handle *handle, 


	handle->pci_dev = pci_info->pci_dev;

	switch (handle->pci_dev->device) {

	case ADF_4XXX_PCI_DEVICE_ID:

		handle->chip_info->sram_visible = false;

		handle->chip_info->nn = false;

		handle->chip_info->lm2lm3 = true;

		handle->chip_info->lm_size = ICP_QAT_UCLO_MAX_LMEM_REG_2X;

		handle->chip_info->icp_rst_csr = ICP_RESET_CPP0;

		handle->chip_info->icp_rst_mask = 0x100015;

		handle->chip_info->glb_clk_enable_csr = ICP_GLOBAL_CLK_ENABLE_CPP0;

		handle->chip_info->misc_ctl_csr = MISC_CONTROL_C4XXX;

		handle->chip_info->wakeup_event_val = 0x80000000;

		handle->chip_info->fw_auth = true;

		handle->chip_info->css_3k = true;

		handle->chip_info->tgroup_share_ustore = true;

		handle->chip_info->fcu_ctl_csr = FCU_CONTROL_4XXX;

		handle->chip_info->fcu_sts_csr = FCU_STATUS_4XXX;

		handle->chip_info->fcu_dram_addr_hi = FCU_DRAM_ADDR_HI_4XXX;

		handle->chip_info->fcu_dram_addr_lo = FCU_DRAM_ADDR_LO_4XXX;

		handle->chip_info->fcu_loaded_ae_csr = FCU_AE_LOADED_4XXX;

		handle->chip_info->fcu_loaded_ae_pos = 0;



		handle->hal_cap_g_ctl_csr_addr_v =

			(void __iomem *)((uintptr_t)misc_bar->virt_addr +

			ICP_QAT_CAP_OFFSET_4XXX);

		handle->hal_cap_ae_xfer_csr_addr_v =

			(void __iomem *)((uintptr_t)misc_bar->virt_addr +

			ICP_QAT_AE_OFFSET_4XXX);

		handle->hal_ep_csr_addr_v =

			(void __iomem *)((uintptr_t)misc_bar->virt_addr +

			ICP_QAT_EP_OFFSET_4XXX);

		handle->hal_cap_ae_local_csr_addr_v =

			(void __iomem *)((uintptr_t)handle->hal_cap_ae_xfer_csr_addr_v

							+ LOCAL_TO_XFER_REG_OFFSET);

		break;

	case PCI_DEVICE_ID_INTEL_QAT_C62X:

	case PCI_DEVICE_ID_INTEL_QAT_C3XXX:

		handle->chip_info->sram_visible = false;
@@ -702,6 +735,8 @@ static int qat_hal_chip_init(struct icp_qat_fw_loader_handle *handle, 
		handle->chip_info->lm2lm3 = false;

		handle->chip_info->lm_size = ICP_QAT_UCLO_MAX_LMEM_REG;

		handle->chip_info->icp_rst_csr = ICP_RESET;

		handle->chip_info->icp_rst_mask = (hw_data->ae_mask << RST_CSR_AE_LSB) |

						  (hw_data->accel_mask << RST_CSR_QAT_LSB);

		handle->chip_info->glb_clk_enable_csr = ICP_GLOBAL_CLK_ENABLE;

		handle->chip_info->misc_ctl_csr = MISC_CONTROL;

		handle->chip_info->wakeup_event_val = WAKEUP_EVENT;
@@ -714,6 +749,18 @@ static int qat_hal_chip_init(struct icp_qat_fw_loader_handle *handle, 
		handle->chip_info->fcu_dram_addr_lo = FCU_DRAM_ADDR_LO;

		handle->chip_info->fcu_loaded_ae_csr = FCU_STATUS;

		handle->chip_info->fcu_loaded_ae_pos = FCU_LOADED_AE_POS;

		handle->hal_cap_g_ctl_csr_addr_v =

			(void __iomem *)((uintptr_t)misc_bar->virt_addr +

			ICP_QAT_CAP_OFFSET);

		handle->hal_cap_ae_xfer_csr_addr_v =

			(void __iomem *)((uintptr_t)misc_bar->virt_addr +

			ICP_QAT_AE_OFFSET);

		handle->hal_ep_csr_addr_v =

			(void __iomem *)((uintptr_t)misc_bar->virt_addr +

			ICP_QAT_EP_OFFSET);

		handle->hal_cap_ae_local_csr_addr_v =

			(void __iomem *)((uintptr_t)handle->hal_cap_ae_xfer_csr_addr_v

			+ LOCAL_TO_XFER_REG_OFFSET);

		break;

	case PCI_DEVICE_ID_INTEL_QAT_DH895XCC:

		handle->chip_info->sram_visible = true;
@@ -721,6 +768,8 @@ static int qat_hal_chip_init(struct icp_qat_fw_loader_handle *handle, 
		handle->chip_info->lm2lm3 = false;

		handle->chip_info->lm_size = ICP_QAT_UCLO_MAX_LMEM_REG;

		handle->chip_info->icp_rst_csr = ICP_RESET;

		handle->chip_info->icp_rst_mask = (hw_data->ae_mask << RST_CSR_AE_LSB) |

						  (hw_data->accel_mask << RST_CSR_QAT_LSB);

		handle->chip_info->glb_clk_enable_csr = ICP_GLOBAL_CLK_ENABLE;

		handle->chip_info->misc_ctl_csr = MISC_CONTROL;

		handle->chip_info->wakeup_event_val = WAKEUP_EVENT;
@@ -733,6 +782,18 @@ static int qat_hal_chip_init(struct icp_qat_fw_loader_handle *handle, 
		handle->chip_info->fcu_dram_addr_lo = 0;

		handle->chip_info->fcu_loaded_ae_csr = 0;

		handle->chip_info->fcu_loaded_ae_pos = 0;

		handle->hal_cap_g_ctl_csr_addr_v =

			(void __iomem *)((uintptr_t)misc_bar->virt_addr +

			ICP_QAT_CAP_OFFSET);

		handle->hal_cap_ae_xfer_csr_addr_v =

			(void __iomem *)((uintptr_t)misc_bar->virt_addr +

			ICP_QAT_AE_OFFSET);

		handle->hal_ep_csr_addr_v =

			(void __iomem *)((uintptr_t)misc_bar->virt_addr +

			ICP_QAT_EP_OFFSET);

		handle->hal_cap_ae_local_csr_addr_v =

			(void __iomem *)((uintptr_t)handle->hal_cap_ae_xfer_csr_addr_v

			+ LOCAL_TO_XFER_REG_OFFSET);

		break;

	default:

		ret = -EINVAL;
@@ -744,22 +805,6 @@ static int qat_hal_chip_init(struct icp_qat_fw_loader_handle *handle, 
			&pci_info->pci_bars[hw_data->get_sram_bar_id(hw_data)];

		handle->hal_sram_addr_v = sram_bar->virt_addr;

	}



	handle->chip_info->icp_rst_mask = (hw_data->ae_mask << RST_CSR_AE_LSB) |

					  (hw_data->accel_mask << RST_CSR_QAT_LSB);

	handle->hal_cap_g_ctl_csr_addr_v =

		(void __iomem *)((uintptr_t)misc_bar->virt_addr +

				 ICP_QAT_CAP_OFFSET);

	handle->hal_cap_ae_xfer_csr_addr_v =

		(void __iomem *)((uintptr_t)misc_bar->virt_addr +

				 ICP_QAT_AE_OFFSET);

	handle->hal_ep_csr_addr_v =

		(void __iomem *)((uintptr_t)misc_bar->virt_addr +

				 ICP_QAT_EP_OFFSET);

	handle->hal_cap_ae_local_csr_addr_v =

		(void __iomem *)((uintptr_t)handle->hal_cap_ae_xfer_csr_addr_v +

				 LOCAL_TO_XFER_REG_OFFSET);

	handle->pci_dev = pci_info->pci_dev;

	handle->hal_handle->revision_id = accel_dev->accel_pci_dev.revid;

	handle->hal_handle->ae_mask = hw_data->ae_mask;

	handle->hal_handle->admin_ae_mask = hw_data->admin_ae_mask;

drivers/crypto/qat/qat_common/qat_uclo.c

+2 −0
Original line number Diff line number Diff line
@@ -728,6 +728,8 @@ qat_uclo_get_dev_type(struct icp_qat_fw_loader_handle *handle) 
		return ICP_QAT_AC_C62X_DEV_TYPE;

	case PCI_DEVICE_ID_INTEL_QAT_C3XXX:

		return ICP_QAT_AC_C3XXX_DEV_TYPE;

	case ADF_4XXX_PCI_DEVICE_ID:

		return ICP_QAT_AC_4XXX_A_DEV_TYPE;

	default:

		pr_err("QAT: unsupported device 0x%x\n",

		       handle->pci_dev->device);