Commit 9bd0bd26 authored by Chuanhong Guo's avatar Chuanhong Guo Committed by Thomas Bogendoerfer
Browse files

MIPS: ralink: drop ralink_clk_init for mt7621 



ralink_clk_init is only called in arch/mips/ralink/clk.c which isn't
compiled for mt7621. And it doesn't export a proper cpu clock.
Drop this unused function.

Signed-off-by: default avatarChuanhong Guo <gch981213@gmail.com>
Signed-off-by: default avatarThomas Bogendoerfer <tsbogend@alpha.franken.de>
parent 38950069

arch/mips/ralink/mt7621.c

+0 −43
Original line number Diff line number Diff line
@@ -20,11 +20,6 @@ 


#include "common.h"



#define SYSC_REG_SYSCFG		0x10

#define SYSC_REG_CPLL_CLKCFG0	0x2c

#define SYSC_REG_CUR_CLK_STS	0x44

#define CPU_CLK_SEL		(BIT(30) | BIT(31))



#define MT7621_GPIO_MODE_UART1		1

#define MT7621_GPIO_MODE_I2C		2

#define MT7621_GPIO_MODE_UART3_MASK	0x3
@@ -115,44 +110,6 @@ phys_addr_t mips_cpc_default_phys_base(void) 
	panic("Cannot detect cpc address");

}



void __init ralink_clk_init(void)

{

	int cpu_fdiv = 0;

	int cpu_ffrac = 0;

	int fbdiv = 0;

	u32 clk_sts, syscfg;

	u8 clk_sel = 0, xtal_mode;

	u32 cpu_clk;



	if ((rt_sysc_r32(SYSC_REG_CPLL_CLKCFG0) & CPU_CLK_SEL) != 0)

		clk_sel = 1;



	switch (clk_sel) {

	case 0:

		clk_sts = rt_sysc_r32(SYSC_REG_CUR_CLK_STS);

		cpu_fdiv = ((clk_sts >> 8) & 0x1F);

		cpu_ffrac = (clk_sts & 0x1F);

		cpu_clk = (500 * cpu_ffrac / cpu_fdiv) * 1000 * 1000;

		break;



	case 1:

		fbdiv = ((rt_sysc_r32(0x648) >> 4) & 0x7F) + 1;

		syscfg = rt_sysc_r32(SYSC_REG_SYSCFG);

		xtal_mode = (syscfg >> 6) & 0x7;

		if (xtal_mode >= 6) {

			/* 25Mhz Xtal */

			cpu_clk = 25 * fbdiv * 1000 * 1000;

		} else if (xtal_mode >= 3) {

			/* 40Mhz Xtal */

			cpu_clk = 40 * fbdiv * 1000 * 1000;

		} else {

			/* 20Mhz Xtal */

			cpu_clk = 20 * fbdiv * 1000 * 1000;

		}

		break;

	}

}



void __init ralink_of_remap(void)

{

	rt_sysc_membase = plat_of_remap_node("mtk,mt7621-sysc");