Commit 9bcf38ed authored by Longfang Liu's avatar Longfang Liu Committed by JiangShui
Browse files

crypto:hisilicon/qm: bugfix queue parameter issue 

driver inclusion
category: feature
bugzilla: https://gitee.com/openeuler/kernel/issues/I79JRM


CVE: NA

----------------------------------------------------------------------

After the queue isolation function is enabled in the BIOS.
If the current default number of queues is used to enable PF,
the default number of queues will be greater than the number of
queues supported by the function set in the BIOS, which will cause
the driver to fail to load.
After modification. If queue isolation is enabled. When the default
queue parameter is larger than the number supported by the function.
The number of enabled queues will be changed to the number supported
by the function.
So that the driver can be loaded normally.

Signed-off-by: default avatarLongfang Liu <liulongfang@huawei.com>
Signed-off-by: default avatarJiangShui Yang <yangjiangshui@h-partners.com>
parent fafc2e95

drivers/crypto/hisilicon/hpre/hpre_main.c

+5 −0
Original line number Diff line number Diff line
@@ -430,8 +430,11 @@ static u32 uacce_mode = UACCE_MODE_NOUACCE; 
module_param_cb(uacce_mode, &hpre_uacce_mode_ops, &uacce_mode, 0444);

MODULE_PARM_DESC(uacce_mode, UACCE_MODE_DESC);



static bool pf_q_num_flag;

static int pf_q_num_set(const char *val, const struct kernel_param *kp)

{

	pf_q_num_flag = true;



	return q_num_set(val, kp, PCI_DEVICE_ID_HUAWEI_HPRE_PF);

}
@@ -1154,6 +1157,8 @@ static int hpre_qm_init(struct hisi_qm *qm, struct pci_dev *pdev) 
		qm->qp_num = pf_q_num;

		qm->debug.curr_qm_qp_num = pf_q_num;

		qm->qm_list = &hpre_devices;

		if (pf_q_num_flag)

			set_bit(QM_MODULE_PARAM, &qm->misc_ctl);

	}



	ret = hisi_qm_init(qm);

drivers/crypto/hisilicon/qm.c

+10 −4
Original line number Diff line number Diff line
@@ -206,7 +206,6 @@ 
#define REMOVE_WAIT_DELAY		10



#define QM_DRIVER_REMOVING		0

#define QM_RST_SCHED			1

#define QM_QOS_PARAM_NUM		2

#define QM_QOS_MAX_VAL			1000

#define QM_QOS_RATE			100
@@ -2962,7 +2961,6 @@ static int hisi_qm_pre_init(struct hisi_qm *qm) 
	mutex_init(&qm->mailbox_lock);

	init_rwsem(&qm->qps_lock);

	qm->qp_in_used = 0;

	qm->misc_ctl = false;

	qm->use_iommu = is_iommu_used(&pdev->dev);

	if (test_bit(QM_SUPPORT_RPM, &qm->caps)) {

		if (!acpi_device_power_manageable(ACPI_COMPANION(&pdev->dev)))
@@ -5253,13 +5251,21 @@ static int qm_get_qp_num(struct hisi_qm *qm) 
	qm->max_qp_num = hisi_qm_get_hw_info(qm, qm_basic_info,

					     QM_FUNC_MAX_QP_CAP, is_db_isolation);



	/* check if qp number is valid */

	if (qm->qp_num > qm->max_qp_num) {

	if (qm->qp_num <= qm->max_qp_num)

		return 0;



	if (test_bit(QM_MODULE_PARAM, &qm->misc_ctl)) {

		/* Check whether the set qp number is valid */

		dev_err(&qm->pdev->dev, "qp num(%u) is more than max qp num(%u)!\n",

			qm->qp_num, qm->max_qp_num);

		return -EINVAL;

	}



	dev_info(&qm->pdev->dev, "Default qp num(%u) is too big, reset it to Function's max qp num(%u)!\n",

		qm->qp_num, qm->max_qp_num);

	qm->qp_num = qm->max_qp_num;

	qm->debug.curr_qm_qp_num = qm->qp_num;



	return 0;

}

drivers/crypto/hisilicon/qm_common.h

+0 −1
Original line number Diff line number Diff line
@@ -4,7 +4,6 @@ 
#define QM_COMMON_H



#define QM_DBG_READ_LEN		256

#define QM_RESETTING		2



struct qm_cqe {

	__le32 rsvd0;

drivers/crypto/hisilicon/sec2/sec_main.c

+5 −0
Original line number Diff line number Diff line
@@ -312,8 +312,11 @@ static int sec_diff_regs_show(struct seq_file *s, void *unused) 
}

DEFINE_SHOW_ATTRIBUTE(sec_diff_regs);



static bool pf_q_num_flag;

static int sec_pf_q_num_set(const char *val, const struct kernel_param *kp)

{

	pf_q_num_flag = true;



	return q_num_set(val, kp, PCI_DEVICE_ID_HUAWEI_SEC_PF);

}
@@ -1121,6 +1124,8 @@ static int sec_qm_init(struct hisi_qm *qm, struct pci_dev *pdev) 
		qm->qp_num = pf_q_num;

		qm->debug.curr_qm_qp_num = pf_q_num;

		qm->qm_list = &sec_devices;

		if (pf_q_num_flag)

			set_bit(QM_MODULE_PARAM, &qm->misc_ctl);

	} else if (qm->fun_type == QM_HW_VF && qm->ver == QM_HW_V1) {

		/*

		 * have no way to get qm configure in VM in v1 hardware,

drivers/crypto/hisilicon/zip/zip_main.c

+5 −0
Original line number Diff line number Diff line
@@ -365,8 +365,11 @@ static u32 uacce_mode = UACCE_MODE_NOUACCE; 
module_param_cb(uacce_mode, &zip_uacce_mode_ops, &uacce_mode, 0444);

MODULE_PARM_DESC(uacce_mode, UACCE_MODE_DESC);



static bool pf_q_num_flag;

static int pf_q_num_set(const char *val, const struct kernel_param *kp)

{

	pf_q_num_flag = true;



	return q_num_set(val, kp, PCI_DEVICE_ID_HUAWEI_ZIP_PF);

}
@@ -1140,6 +1143,8 @@ static int hisi_zip_qm_init(struct hisi_qm *qm, struct pci_dev *pdev) 
		qm->qp_num = pf_q_num;

		qm->debug.curr_qm_qp_num = pf_q_num;

		qm->qm_list = &zip_devices;

		if (pf_q_num_flag)

			set_bit(QM_MODULE_PARAM, &qm->misc_ctl);

	} else if (qm->fun_type == QM_HW_VF && qm->ver == QM_HW_V1) {

		/*

		 * have no way to get qm configure in VM in v1 hardware,