Commit 9b71e1c9 authored by Ben Widawsky's avatar Ben Widawsky Committed by Dan Williams
Browse files

cxl/core/port: Add endpoint decoders 



Recall that a CXL Port is any object that publishes a CXL HDM Decoder
Capability structure. That is Host Bridge and Switches that have been
enabled so far. Now, add decoder support to the 'endpoint' CXL Ports
registered by the cxl_mem driver. They mostly share the same enumeration
as Bridges and Switches, but witout a target list. The target of
endpoint decode is device-internal DPA space, not another downstream
port.

Signed-off-by: default avatarBen Widawsky <ben.widawsky@intel.com>
Reviewed-by: default avatarJonathan Cameron <Jonathan.Cameron@huawei.com>
[djbw: clarify changelog, hookup enumeration in the port driver]
Link: https://lore.kernel.org/r/164386092069.765089.14895687988217608642.stgit@dwillia2-desk3.amr.corp.intel.com


Signed-off-by: default avatarDan Williams <dan.j.williams@intel.com>
parent 8aea0ef1

drivers/cxl/core/hdm.c

+7 −1
Original line number Diff line number Diff line
@@ -186,6 +186,9 @@ static void init_hdm_decoder(struct cxl_decoder *cxld, int *target_map, 
	else

		cxld->target_type = CXL_DECODER_ACCELERATOR;



	if (is_cxl_endpoint(to_cxl_port(cxld->dev.parent)))

		return;



	target_list.value =

		ioread64_hi_lo(hdm + CXL_HDM_DECODER0_TL_LOW(which));

	for (i = 0; i < cxld->interleave_ways; i++)
@@ -225,6 +228,9 @@ int devm_cxl_enumerate_decoders(struct cxl_hdm *cxlhdm) 
		int rc, target_count = cxlhdm->target_count;

		struct cxl_decoder *cxld;



		if (is_cxl_endpoint(port))

			cxld = cxl_endpoint_decoder_alloc(port);

		else

			cxld = cxl_switch_decoder_alloc(port, target_count);

		if (IS_ERR(cxld)) {

			dev_warn(&port->dev,

drivers/cxl/core/port.c

+56 −7
Original line number Diff line number Diff line
@@ -228,6 +228,22 @@ static const struct attribute_group *cxl_decoder_switch_attribute_groups[] = { 
	NULL,

};



static struct attribute *cxl_decoder_endpoint_attrs[] = {

	&dev_attr_target_type.attr,

	NULL,

};



static struct attribute_group cxl_decoder_endpoint_attribute_group = {

	.attrs = cxl_decoder_endpoint_attrs,

};



static const struct attribute_group *cxl_decoder_endpoint_attribute_groups[] = {

	&cxl_decoder_base_attribute_group,

	&cxl_decoder_endpoint_attribute_group,

	&cxl_base_attribute_group,

	NULL,

};



static void cxl_decoder_release(struct device *dev)

{

	struct cxl_decoder *cxld = to_cxl_decoder(dev);
@@ -237,6 +253,12 @@ static void cxl_decoder_release(struct device *dev) 
	kfree(cxld);

}



static const struct device_type cxl_decoder_endpoint_type = {

	.name = "cxl_decoder_endpoint",

	.release = cxl_decoder_release,

	.groups = cxl_decoder_endpoint_attribute_groups,

};



static const struct device_type cxl_decoder_switch_type = {

	.name = "cxl_decoder_switch",

	.release = cxl_decoder_release,
@@ -249,6 +271,11 @@ static const struct device_type cxl_decoder_root_type = { 
	.groups = cxl_decoder_root_attribute_groups,

};



static bool is_endpoint_decoder(struct device *dev)

{

	return dev->type == &cxl_decoder_endpoint_type;

}



bool is_root_decoder(struct device *dev)

{

	return dev->type == &cxl_decoder_root_type;
@@ -1129,7 +1156,9 @@ static int decoder_populate_targets(struct cxl_decoder *cxld, 
 * cxl_decoder_alloc - Allocate a new CXL decoder

 * @port: owning port of this decoder

 * @nr_targets: downstream targets accessible by this decoder. All upstream

 *		ports and root ports must have at least 1 target.

 *		ports and root ports must have at least 1 target. Endpoint

 *		devices will have 0 targets. Callers wishing to register an

 *		endpoint device should specify 0.

 *

 * A port should contain one or more decoders. Each of those decoders enable

 * some address space for CXL.mem utilization. A decoder is expected to be
@@ -1145,7 +1174,7 @@ static struct cxl_decoder *cxl_decoder_alloc(struct cxl_port *port, 
	struct device *dev;

	int rc = 0;



	if (nr_targets > CXL_DECODER_MAX_INTERLEAVE || nr_targets == 0)

	if (nr_targets > CXL_DECODER_MAX_INTERLEAVE)

		return ERR_PTR(-EINVAL);



	cxld = kzalloc(struct_size(cxld, target, nr_targets), GFP_KERNEL);
@@ -1166,6 +1195,8 @@ static struct cxl_decoder *cxl_decoder_alloc(struct cxl_port *port, 
	dev->bus = &cxl_bus_type;

	if (is_cxl_root(port))

		cxld->dev.type = &cxl_decoder_root_type;

	else if (is_cxl_endpoint(port))

		cxld->dev.type = &cxl_decoder_endpoint_type;

	else

		cxld->dev.type = &cxl_decoder_switch_type;
@@ -1215,13 +1246,28 @@ EXPORT_SYMBOL_NS_GPL(cxl_root_decoder_alloc, CXL); 
struct cxl_decoder *cxl_switch_decoder_alloc(struct cxl_port *port,

					     unsigned int nr_targets)

{

	if (is_cxl_root(port))

	if (is_cxl_root(port) || is_cxl_endpoint(port))

		return ERR_PTR(-EINVAL);



	return cxl_decoder_alloc(port, nr_targets);

}

EXPORT_SYMBOL_NS_GPL(cxl_switch_decoder_alloc, CXL);



/**

 * cxl_endpoint_decoder_alloc - Allocate an endpoint decoder

 * @port: owning port of this decoder

 *

 * Return: A new cxl decoder to be registered by cxl_decoder_add()

 */

struct cxl_decoder *cxl_endpoint_decoder_alloc(struct cxl_port *port)

{

	if (!is_cxl_endpoint(port))

		return ERR_PTR(-EINVAL);



	return cxl_decoder_alloc(port, 0);

}

EXPORT_SYMBOL_NS_GPL(cxl_endpoint_decoder_alloc, CXL);



/**

 * cxl_decoder_add_locked - Add a decoder with targets

 * @cxld: The cxl decoder allocated by cxl_decoder_alloc()
@@ -1256,12 +1302,15 @@ int cxl_decoder_add_locked(struct cxl_decoder *cxld, int *target_map) 
	if (cxld->interleave_ways < 1)

		return -EINVAL;



	dev = &cxld->dev;



	port = to_cxl_port(cxld->dev.parent);

	if (!is_endpoint_decoder(dev)) {

		rc = decoder_populate_targets(cxld, port, target_map);

		if (rc)

			return rc;

	}



	dev = &cxld->dev;

	rc = dev_set_name(dev, "decoder%d.%d", port->id, cxld->id);

	if (rc)

		return rc;

drivers/cxl/cxl.h

+1 −0
Original line number Diff line number Diff line
@@ -346,6 +346,7 @@ struct cxl_decoder *cxl_root_decoder_alloc(struct cxl_port *port, 
struct cxl_decoder *cxl_switch_decoder_alloc(struct cxl_port *port,

					     unsigned int nr_targets);

int cxl_decoder_add(struct cxl_decoder *cxld, int *target_map);

struct cxl_decoder *cxl_endpoint_decoder_alloc(struct cxl_port *port);

int cxl_decoder_add_locked(struct cxl_decoder *cxld, int *target_map);

int cxl_decoder_autoremove(struct device *host, struct cxl_decoder *cxld);

int cxl_endpoint_autoremove(struct cxl_memdev *cxlmd, struct cxl_port *endpoint);

drivers/cxl/port.c

+9 −8
Original line number Diff line number Diff line
@@ -40,15 +40,16 @@ static int cxl_port_probe(struct device *dev) 
		struct cxl_memdev *cxlmd = to_cxl_memdev(port->uport);



		get_device(&cxlmd->dev);

		return devm_add_action_or_reset(dev, schedule_detach, cxlmd);

	}



		rc = devm_add_action_or_reset(dev, schedule_detach, cxlmd);

		if (rc)

			return rc;

	} else {

		rc = devm_cxl_port_enumerate_dports(port);

		if (rc < 0)

			return rc;



		if (rc == 1)

			return devm_cxl_add_passthrough_decoder(port);

	}



	cxlhdm = devm_cxl_setup_hdm(port);

	if (IS_ERR(cxlhdm))