Commit 9b5f77ef authored by Dan Williams's avatar Dan Williams
Browse files

cxl/pci: Remove endian confusion 



readl() already handles endian conversion. That's the main difference
between readl() and __raw_readl(). This is benign on little-endian
systems, but big endian systems will end up byte-swabbing twice.

Fixes: 2905cb52 ("cxl/pci: Add (hopeful) error handling support")
Cc: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Cc: Dave Jiang <dave.jiang@intel.com>
Reviewed-by: default avatarDave Jiang <dave.jiang@intel.com>
Reviewed-by: default avatarJonathan Cameron <Jonathan.Cameron@huawei.com>
Reviewed-by: default avatarIra Weiny <ira.weiny@intel.com>
Link: https://lore.kernel.org/r/167030092025.4045167.10651070153523351093.stgit@dwillia2-xfh.jf.intel.com


Signed-off-by: default avatarDan Williams <dan.j.williams@intel.com>
parent 372ab3bc

drivers/cxl/pci.c

+3 −4
Original line number Diff line number Diff line
@@ -548,15 +548,14 @@ static bool cxl_report_and_clear(struct cxl_dev_state *cxlds) 
		return false;



	addr = cxlds->regs.ras + CXL_RAS_UNCORRECTABLE_STATUS_OFFSET;

	status = le32_to_cpu((__force __le32)readl(addr));

	status = readl(addr);

	if (!(status & CXL_RAS_UNCORRECTABLE_STATUS_MASK))

		return false;



	/* If multiple errors, log header points to first error from ctrl reg */

	if (hweight32(status) > 1) {

		addr = cxlds->regs.ras + CXL_RAS_CAP_CONTROL_OFFSET;

		fe = BIT(le32_to_cpu((__force __le32)readl(addr)) &

				     CXL_RAS_CAP_CONTROL_FE_MASK);

		fe = BIT(FIELD_GET(CXL_RAS_CAP_CONTROL_FE_MASK, readl(addr)));

	} else {

		fe = status;

	}
@@ -641,7 +640,7 @@ static void cxl_cor_error_detected(struct pci_dev *pdev) 
		return;



	addr = cxlds->regs.ras + CXL_RAS_CORRECTABLE_STATUS_OFFSET;

	status = le32_to_cpu(readl(addr));

	status = readl(addr);

	if (status & CXL_RAS_CORRECTABLE_STATUS_MASK) {

		writel(status & CXL_RAS_CORRECTABLE_STATUS_MASK, addr);

		trace_cxl_aer_correctable_error(dev, status);