Commit 9b424083 authored by Ian Rogers's avatar Ian Rogers Committed by Arnaldo Carvalho de Melo
Browse files

perf vendor events intel: Refresh snowridgex events 

Update the snowridgex events using the new tooling from:

  https://github.com/intel/perfmon



The events are unchanged but unused json values are removed and
descriptions improved. This increases consistency across the json
files.

Signed-off-by: default avatarIan Rogers <irogers@google.com>
Acked-by: default avatarKan Liang <kan.liang@linux.intel.com>
Cc: Adrian Hunter <adrian.hunter@intel.com>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Caleb Biggers <caleb.biggers@intel.com>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: Jiri Olsa <jolsa@kernel.org>
Cc: John Garry <john.g.garry@oracle.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Namhyung Kim <namhyung@kernel.org>
Cc: Perry Taylor <perry.taylor@intel.com>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Stephane Eranian <eranian@google.com>
Cc: Xing Zhengjun <zhengjun.xing@linux.intel.com>
Link: https://lore.kernel.org/r/20221215065510.1621979-20-irogers@google.com


Signed-off-by: default avatarArnaldo Carvalho de Melo <acme@redhat.com>
parent ecabdc6a

tools/perf/pmu-events/arch/x86/snowridgex/cache.json

+0 −252

File changed.

Preview size limit exceeded, changes collapsed.

tools/perf/pmu-events/arch/x86/snowridgex/floating-point.json

+0 −11
Original line number Diff line number Diff line 
[

    {

        "BriefDescription": "Counts the number of cycles the floating point divider is busy.",

        "CollectPEBSRecord": "2",

        "Counter": "0,1,2,3",

        "EventCode": "0xcd",

        "EventName": "CYCLES_DIV_BUSY.FPDIV",

        "PDIR_COUNTER": "NA",

        "PEBScounters": "0,1,2,3",

        "PublicDescription": "Counts the number of cycles the floating point divider is busy.  Does not imply a stall waiting for the divider.",

        "SampleAfterValue": "200003",

        "UMask": "0x2"

    },

    {

        "BriefDescription": "Counts the number of floating point operations retired that required microcode assist.",

        "CollectPEBSRecord": "2",

        "Counter": "0,1,2,3",

        "EventCode": "0xc3",

        "EventName": "MACHINE_CLEARS.FP_ASSIST",

        "PDIR_COUNTER": "NA",

        "PEBScounters": "0,1,2,3",

        "PublicDescription": "Counts the number of floating point operations retired that required microcode assist, which is not a reflection of the number of FP operations, instructions or uops.",

        "SampleAfterValue": "20003",

        "UMask": "0x4"

    },

    {

        "BriefDescription": "Counts the number of floating point divide uops retired (x87 and SSE, including x87 sqrt).",

        "CollectPEBSRecord": "2",

        "Counter": "0,1,2,3",

        "EventCode": "0xc2",

        "EventName": "UOPS_RETIRED.FPDIV",

        "PEBS": "1",

        "PEBScounters": "0,1,2,3",

        "SampleAfterValue": "2000003",

        "UMask": "0x8"

    }

tools/perf/pmu-events/arch/x86/snowridgex/frontend.json

+0 −36
Original line number Diff line number Diff line 
[

    {

        "BriefDescription": "Counts the total number of BACLEARS due to all branch types including conditional and unconditional jumps, returns, and indirect branches.",

        "CollectPEBSRecord": "2",

        "Counter": "0,1,2,3",

        "EventCode": "0xe6",

        "EventName": "BACLEARS.ANY",

        "PDIR_COUNTER": "NA",

        "PEBScounters": "0,1,2,3",

        "PublicDescription": "Counts the total number of BACLEARS, which occur when the Branch Target Buffer (BTB) prediction or lack thereof, was corrected by a later branch predictor in the frontend.  Includes BACLEARS due to all branch types including conditional and unconditional jumps, returns, and indirect branches.",

        "SampleAfterValue": "200003",

        "UMask": "0x1"

    },

    {

        "BriefDescription": "Counts the number of BACLEARS due to a conditional jump.",

        "CollectPEBSRecord": "2",

        "Counter": "0,1,2,3",

        "EventCode": "0xe6",

        "EventName": "BACLEARS.COND",

        "PDIR_COUNTER": "NA",

        "PEBScounters": "0,1,2,3",

        "SampleAfterValue": "200003",

        "UMask": "0x10"

    },

    {

        "BriefDescription": "Counts the number of BACLEARS due to an indirect branch.",

        "CollectPEBSRecord": "2",

        "Counter": "0,1,2,3",

        "EventCode": "0xe6",

        "EventName": "BACLEARS.INDIRECT",

        "PDIR_COUNTER": "NA",

        "PEBScounters": "0,1,2,3",

        "SampleAfterValue": "200003",

        "UMask": "0x2"

    },

    {

        "BriefDescription": "Counts the number of BACLEARS due to a return branch.",

        "CollectPEBSRecord": "2",

        "Counter": "0,1,2,3",

        "EventCode": "0xe6",

        "EventName": "BACLEARS.RETURN",

        "PDIR_COUNTER": "NA",

        "PEBScounters": "0,1,2,3",

        "SampleAfterValue": "200003",

        "UMask": "0x8"

    },

    {

        "BriefDescription": "Counts the number of BACLEARS due to a direct, unconditional jump.",

        "CollectPEBSRecord": "2",

        "Counter": "0,1,2,3",

        "EventCode": "0xe6",

        "EventName": "BACLEARS.UNCOND",

        "PDIR_COUNTER": "NA",

        "PEBScounters": "0,1,2,3",

        "SampleAfterValue": "200003",

        "UMask": "0x4"

    },

    {

        "BriefDescription": "Counts the number of times a decode restriction reduces the decode throughput due to wrong instruction length prediction.",

        "CollectPEBSRecord": "2",

        "Counter": "0,1,2,3",

        "EventCode": "0xe9",

        "EventName": "DECODE_RESTRICTION.PREDECODE_WRONG",

        "PDIR_COUNTER": "NA",

        "PEBScounters": "0,1,2,3",

        "SampleAfterValue": "200003",

        "UMask": "0x1"

    },

    {

        "BriefDescription": "Counts the number of requests to the instruction cache for one or more bytes of a cache line.",

        "CollectPEBSRecord": "2",

        "Counter": "0,1,2,3",

        "EventCode": "0x80",

        "EventName": "ICACHE.ACCESSES",

        "PDIR_COUNTER": "NA",

        "PEBScounters": "0,1,2,3",

        "PublicDescription": "Counts the total number of requests to the instruction cache.  The event only counts new cache line accesses, so that multiple back to back fetches to the exact same cache line or byte chunk count as one.  Specifically, the event counts when accesses from sequential code crosses the cache line boundary, or when a branch target is moved to a new line or to a non-sequential byte chunk of the same line.",

        "SampleAfterValue": "200003",

        "UMask": "0x3"

    },

    {

        "BriefDescription": "Counts the number of instruction cache hits.",

        "CollectPEBSRecord": "2",

        "Counter": "0,1,2,3",

        "EventCode": "0x80",

        "EventName": "ICACHE.HIT",

        "PDIR_COUNTER": "NA",

        "PEBScounters": "0,1,2,3",

        "PublicDescription": "Counts the number of requests that hit in the instruction cache.  The event only counts new cache line accesses, so that multiple back to back fetches to the exact same cache line and byte chunk count as one.  Specifically, the event counts when accesses from sequential code crosses the cache line boundary, or when a branch target is moved to a new line or to a non-sequential byte chunk of the same line.",

        "SampleAfterValue": "200003",

        "UMask": "0x1"

    },

    {

        "BriefDescription": "Counts the number of instruction cache misses.",

        "CollectPEBSRecord": "2",

        "Counter": "0,1,2,3",

        "EventCode": "0x80",

        "EventName": "ICACHE.MISSES",

        "PDIR_COUNTER": "NA",

        "PEBScounters": "0,1,2,3",

        "PublicDescription": "Counts the number of missed requests to the instruction cache.  The event only counts new cache line accesses, so that multiple back to back fetches to the exact same cache line and byte chunk count as one.  Specifically, the event counts when accesses from sequential code crosses the cache line boundary, or when a branch target is moved to a new line or to a non-sequential byte chunk of the same line.",

        "SampleAfterValue": "200003",

        "UMask": "0x2"

tools/perf/pmu-events/arch/x86/snowridgex/memory.json

+0 −84
Original line number Diff line number Diff line 
[

    {

        "BriefDescription": "Counts the number of machine clears due to memory ordering caused by a snoop from an external agent. Does not count internally generated machine clears such as those due to memory disambiguation.",

        "CollectPEBSRecord": "2",

        "Counter": "0,1,2,3",

        "EventCode": "0xc3",

        "EventName": "MACHINE_CLEARS.MEMORY_ORDERING",

        "PDIR_COUNTER": "NA",

        "PEBScounters": "0,1,2,3",

        "SampleAfterValue": "20003",

        "UMask": "0x2"

    },

    {

        "BriefDescription": "Counts the number of misaligned load uops that are 4K page splits.",

        "CollectPEBSRecord": "2",

        "Counter": "0,1,2,3",

        "EventCode": "0x13",

        "EventName": "MISALIGN_MEM_REF.LOAD_PAGE_SPLIT",

        "PEBS": "1",

        "PEBScounters": "0,1,2,3",

        "SampleAfterValue": "200003",

        "UMask": "0x2"

    },

    {

        "BriefDescription": "Counts the number of misaligned store uops that are 4K page splits.",

        "CollectPEBSRecord": "2",

        "Counter": "0,1,2,3",

        "EventCode": "0x13",

        "EventName": "MISALIGN_MEM_REF.STORE_PAGE_SPLIT",

        "PEBS": "1",

        "PEBScounters": "0,1,2,3",

        "SampleAfterValue": "200003",

        "UMask": "0x4"

    },

    {

        "BriefDescription": "Counts all code reads that were not supplied by the L3 cache.",

        "Counter": "0,1,2,3",

        "EventCode": "0XB7",

        "EventName": "OCR.ALL_CODE_RD.L3_MISS",

        "MSRIndex": "0x1a6,0x1a7",

        "MSRValue": "0x2184000044",

        "Offcore": "1",

        "SampleAfterValue": "100003",

        "UMask": "0x1"

    },

    {

        "BriefDescription": "Counts all code reads that were not supplied by the L3 cache.",

        "Counter": "0,1,2,3",

        "EventCode": "0XB7",

        "EventName": "OCR.ALL_CODE_RD.L3_MISS_LOCAL",

        "MSRIndex": "0x1a6,0x1a7",

        "MSRValue": "0x2184000044",

        "Offcore": "1",

        "SampleAfterValue": "100003",

        "UMask": "0x1"

    },

    {

        "BriefDescription": "Counts modified writebacks from L1 cache and L2 cache that were not supplied by the L3 cache.",

        "Counter": "0,1,2,3",

        "EventCode": "0XB7",

        "EventName": "OCR.COREWB_M.L3_MISS",

        "MSRIndex": "0x1a6,0x1a7",

        "MSRValue": "0x3002184000000",

        "Offcore": "1",

        "SampleAfterValue": "100003",

        "UMask": "0x1"

    },

    {

        "BriefDescription": "Counts modified writebacks from L1 cache and L2 cache that were not supplied by the L3 cache.",

        "Counter": "0,1,2,3",

        "EventCode": "0XB7",

        "EventName": "OCR.COREWB_M.L3_MISS_LOCAL",

        "MSRIndex": "0x1a6,0x1a7",

        "MSRValue": "0x3002184000000",

        "Offcore": "1",

        "SampleAfterValue": "100003",

        "UMask": "0x1"

    },

    {

        "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that were not supplied by the L3 cache.",

        "Counter": "0,1,2,3",

        "EventCode": "0XB7",

        "EventName": "OCR.DEMAND_CODE_RD.L3_MISS",

        "MSRIndex": "0x1a6,0x1a7",

        "MSRValue": "0x2184000004",

        "Offcore": "1",

        "SampleAfterValue": "100003",

        "UMask": "0x1"

    },

    {

        "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that were not supplied by the L3 cache.",

        "Counter": "0,1,2,3",

        "EventCode": "0XB7",

        "EventName": "OCR.DEMAND_CODE_RD.L3_MISS_LOCAL",

        "MSRIndex": "0x1a6,0x1a7",

        "MSRValue": "0x2184000004",

        "Offcore": "1",

        "SampleAfterValue": "100003",

        "UMask": "0x1"

    },

    {

        "BriefDescription": "Counts cacheable demand data reads, L1 data cache hardware prefetches and software prefetches (except PREFETCHW) that were not supplied by the L3 cache.",

        "Counter": "0,1,2,3",

        "EventCode": "0XB7",

        "EventName": "OCR.DEMAND_DATA_AND_L1PF_RD.L3_MISS",

        "MSRIndex": "0x1a6,0x1a7",

        "MSRValue": "0x2184000001",

        "Offcore": "1",

        "SampleAfterValue": "100003",

        "UMask": "0x1"

    },

    {

        "BriefDescription": "Counts cacheable demand data reads, L1 data cache hardware prefetches and software prefetches (except PREFETCHW) that were not supplied by the L3 cache.",

        "Counter": "0,1,2,3",

        "EventCode": "0XB7",

        "EventName": "OCR.DEMAND_DATA_AND_L1PF_RD.L3_MISS_LOCAL",

        "MSRIndex": "0x1a6,0x1a7",

        "MSRValue": "0x2184000001",

        "Offcore": "1",

        "SampleAfterValue": "100003",

        "UMask": "0x1"

    },

    {

        "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_AND_L1PF_RD.L3_MISS",

        "Counter": "0,1,2,3",

        "EventCode": "0XB7",

        "EventName": "OCR.DEMAND_DATA_RD.L3_MISS",

        "MSRIndex": "0x1a6,0x1a7",

        "MSRValue": "0x2184000001",

        "Offcore": "1",

        "SampleAfterValue": "100003",

        "UMask": "0x1"

    },

    {

        "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_AND_L1PF_RD.L3_MISS_LOCAL",

        "Counter": "0,1,2,3",

        "EventCode": "0XB7",

        "EventName": "OCR.DEMAND_DATA_RD.L3_MISS_LOCAL",

        "MSRIndex": "0x1a6,0x1a7",

        "MSRValue": "0x2184000001",

        "Offcore": "1",

        "SampleAfterValue": "100003",

        "UMask": "0x1"

    },

    {

        "BriefDescription": "Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that were not supplied by the L3 cache.",

        "Counter": "0,1,2,3",

        "EventCode": "0XB7",

        "EventName": "OCR.DEMAND_RFO.L3_MISS",

        "MSRIndex": "0x1a6,0x1a7",

        "MSRValue": "0x2184000002",

        "Offcore": "1",

        "SampleAfterValue": "100003",

        "UMask": "0x1"

    },

    {

        "BriefDescription": "Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that were not supplied by the L3 cache.",

        "Counter": "0,1,2,3",

        "EventCode": "0XB7",

        "EventName": "OCR.DEMAND_RFO.L3_MISS_LOCAL",

        "MSRIndex": "0x1a6,0x1a7",

        "MSRValue": "0x2184000002",

        "Offcore": "1",

        "SampleAfterValue": "100003",

        "UMask": "0x1"

    },

    {

        "BriefDescription": "Counts streaming stores which modify a full 64 byte cacheline that were not supplied by the L3 cache.",

        "Counter": "0,1,2,3",

        "EventCode": "0XB7",

        "EventName": "OCR.FULL_STREAMING_WR.L3_MISS",

        "MSRIndex": "0x1a6,0x1a7",

        "MSRValue": "0x802184000000",

        "Offcore": "1",

        "SampleAfterValue": "100003",

        "UMask": "0x1"

    },

    {

        "BriefDescription": "Counts streaming stores which modify a full 64 byte cacheline that were not supplied by the L3 cache.",

        "Counter": "0,1,2,3",

        "EventCode": "0XB7",

        "EventName": "OCR.FULL_STREAMING_WR.L3_MISS_LOCAL",

        "MSRIndex": "0x1a6,0x1a7",

        "MSRValue": "0x802184000000",

        "Offcore": "1",

        "SampleAfterValue": "100003",

        "UMask": "0x1"

    },

    {

        "BriefDescription": "Counts L2 cache hardware prefetch code reads (written to the L2 cache only) that were not supplied by the L3 cache.",

        "Counter": "0,1,2,3",

        "EventCode": "0XB7",

        "EventName": "OCR.HWPF_L2_CODE_RD.L3_MISS",

        "MSRIndex": "0x1a6,0x1a7",

        "MSRValue": "0x2184000040",

        "Offcore": "1",

        "SampleAfterValue": "100003",

        "UMask": "0x1"

    },

    {

        "BriefDescription": "Counts L2 cache hardware prefetch code reads (written to the L2 cache only) that were not supplied by the L3 cache.",

        "Counter": "0,1,2,3",

        "EventCode": "0XB7",

        "EventName": "OCR.HWPF_L2_CODE_RD.L3_MISS_LOCAL",

        "MSRIndex": "0x1a6,0x1a7",

        "MSRValue": "0x2184000040",

        "Offcore": "1",

        "SampleAfterValue": "100003",

        "UMask": "0x1"

    },

    {

        "BriefDescription": "Counts L2 cache hardware prefetch data reads (written to the L2 cache only) that were not supplied by the L3 cache.",

        "Counter": "0,1,2,3",

        "EventCode": "0XB7",

        "EventName": "OCR.HWPF_L2_DATA_RD.L3_MISS",

        "MSRIndex": "0x1a6,0x1a7",

        "MSRValue": "0x2184000010",

        "Offcore": "1",

        "SampleAfterValue": "100003",

        "UMask": "0x1"

    },

    {

        "BriefDescription": "Counts L2 cache hardware prefetch data reads (written to the L2 cache only) that were not supplied by the L3 cache.",

        "Counter": "0,1,2,3",

        "EventCode": "0XB7",

        "EventName": "OCR.HWPF_L2_DATA_RD.L3_MISS_LOCAL",

        "MSRIndex": "0x1a6,0x1a7",

        "MSRValue": "0x2184000010",

        "Offcore": "1",

        "SampleAfterValue": "100003",

        "UMask": "0x1"

    },

    {

        "BriefDescription": "Counts L2 cache hardware prefetch RFOs (written to the L2 cache only) that were not supplied by the L3 cache.",

        "Counter": "0,1,2,3",

        "EventCode": "0XB7",

        "EventName": "OCR.HWPF_L2_RFO.L3_MISS",

        "MSRIndex": "0x1a6,0x1a7",

        "MSRValue": "0x2184000020",

        "Offcore": "1",

        "SampleAfterValue": "100003",

        "UMask": "0x1"

    },

    {

        "BriefDescription": "Counts L2 cache hardware prefetch RFOs (written to the L2 cache only) that were not supplied by the L3 cache.",

        "Counter": "0,1,2,3",

        "EventCode": "0XB7",

        "EventName": "OCR.HWPF_L2_RFO.L3_MISS_LOCAL",

        "MSRIndex": "0x1a6,0x1a7",

        "MSRValue": "0x2184000020",

        "Offcore": "1",

        "SampleAfterValue": "100003",

        "UMask": "0x1"

    },

    {

        "BriefDescription": "Counts modified writebacks from L1 cache that miss the L2 cache that were not supplied by the L3 cache.",

        "Counter": "0,1,2,3",

        "EventCode": "0XB7",

        "EventName": "OCR.L1WB_M.L3_MISS",

        "MSRIndex": "0x1a6,0x1a7",

        "MSRValue": "0x1002184000000",

        "Offcore": "1",

        "SampleAfterValue": "100003",

        "UMask": "0x1"

    },

    {

        "BriefDescription": "Counts modified writebacks from L1 cache that miss the L2 cache that were not supplied by the L3 cache.",

        "Counter": "0,1,2,3",

        "EventCode": "0XB7",

        "EventName": "OCR.L1WB_M.L3_MISS_LOCAL",

        "MSRIndex": "0x1a6,0x1a7",

        "MSRValue": "0x1002184000000",

        "Offcore": "1",

        "SampleAfterValue": "100003",

        "UMask": "0x1"

    },

    {

        "BriefDescription": "Counts modified writeBacks from L2 cache that miss the L3 cache that were not supplied by the L3 cache.",

        "Counter": "0,1,2,3",

        "EventCode": "0XB7",

        "EventName": "OCR.L2WB_M.L3_MISS",

        "MSRIndex": "0x1a6,0x1a7",

        "MSRValue": "0x2002184000000",

        "Offcore": "1",

        "SampleAfterValue": "100003",

        "UMask": "0x1"

    },

    {

        "BriefDescription": "Counts modified writeBacks from L2 cache that miss the L3 cache that were not supplied by the L3 cache.",

        "Counter": "0,1,2,3",

        "EventCode": "0XB7",

        "EventName": "OCR.L2WB_M.L3_MISS_LOCAL",

        "MSRIndex": "0x1a6,0x1a7",

        "MSRValue": "0x2002184000000",

        "Offcore": "1",

        "SampleAfterValue": "100003",

        "UMask": "0x1"

    },

    {

        "BriefDescription": "Counts miscellaneous requests, such as I/O accesses, that were not supplied by the L3 cache.",

        "Counter": "0,1,2,3",

        "EventCode": "0XB7",

        "EventName": "OCR.OTHER.L3_MISS",

        "MSRIndex": "0x1a6,0x1a7",

        "MSRValue": "0x2184008000",

        "Offcore": "1",

        "SampleAfterValue": "100003",

        "UMask": "0x1"

    },

    {

        "BriefDescription": "Counts miscellaneous requests, such as I/O accesses, that were not supplied by the L3 cache.",

        "Counter": "0,1,2,3",

        "EventCode": "0XB7",

        "EventName": "OCR.OTHER.L3_MISS_LOCAL",

        "MSRIndex": "0x1a6,0x1a7",

        "MSRValue": "0x2184008000",

        "Offcore": "1",

        "SampleAfterValue": "100003",

        "UMask": "0x1"

    },

    {

        "BriefDescription": "Counts streaming stores which modify only part of a 64 byte cacheline that were not supplied by the L3 cache.",

        "Counter": "0,1,2,3",

        "EventCode": "0XB7",

        "EventName": "OCR.PARTIAL_STREAMING_WR.L3_MISS",

        "MSRIndex": "0x1a6,0x1a7",

        "MSRValue": "0x402184000000",

        "Offcore": "1",

        "SampleAfterValue": "100003",

        "UMask": "0x1"

    },

    {

        "BriefDescription": "Counts streaming stores which modify only part of a 64 byte cacheline that were not supplied by the L3 cache.",

        "Counter": "0,1,2,3",

        "EventCode": "0XB7",

        "EventName": "OCR.PARTIAL_STREAMING_WR.L3_MISS_LOCAL",

        "MSRIndex": "0x1a6,0x1a7",

        "MSRValue": "0x402184000000",

        "Offcore": "1",

        "SampleAfterValue": "100003",

        "UMask": "0x1"

    },

    {

        "BriefDescription": "Counts all hardware and software prefetches that were not supplied by the L3 cache.",

        "Counter": "0,1,2,3",

        "EventCode": "0XB7",

        "EventName": "OCR.PREFETCHES.L3_MISS",

        "MSRIndex": "0x1a6,0x1a7",

        "MSRValue": "0x2184000470",

        "Offcore": "1",

        "SampleAfterValue": "100003",

        "UMask": "0x1"

    },

    {

        "BriefDescription": "Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were not supplied by the L3 cache.",

        "Counter": "0,1,2,3",

        "EventCode": "0XB7",

        "EventName": "OCR.READS_TO_CORE.L3_MISS",

        "MSRIndex": "0x1a6,0x1a7",

        "MSRValue": "0x2184000477",

        "Offcore": "1",

        "SampleAfterValue": "100003",

        "UMask": "0x1"

    },

    {

        "BriefDescription": "Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were not supplied by the L3 cache.",

        "Counter": "0,1,2,3",

        "EventCode": "0XB7",

        "EventName": "OCR.READS_TO_CORE.L3_MISS_LOCAL",

        "MSRIndex": "0x1a6,0x1a7",

        "MSRValue": "0x2184000477",

        "Offcore": "1",

        "SampleAfterValue": "100003",

        "UMask": "0x1"

    },

    {

        "BriefDescription": "Counts streaming stores that were not supplied by the L3 cache.",

        "Counter": "0,1,2,3",

        "EventCode": "0XB7",

        "EventName": "OCR.STREAMING_WR.L3_MISS",

        "MSRIndex": "0x1a6,0x1a7",

        "MSRValue": "0x2184000800",

        "Offcore": "1",

        "SampleAfterValue": "100003",

        "UMask": "0x1"

    },

    {

        "BriefDescription": "Counts streaming stores that were not supplied by the L3 cache.",

        "Counter": "0,1,2,3",

        "EventCode": "0XB7",

        "EventName": "OCR.STREAMING_WR.L3_MISS_LOCAL",

        "MSRIndex": "0x1a6,0x1a7",

        "MSRValue": "0x2184000800",

        "Offcore": "1",

        "SampleAfterValue": "100003",

        "UMask": "0x1"

    },

    {

        "BriefDescription": "Counts uncached memory reads that were not supplied by the L3 cache.",

        "Counter": "0,1,2,3",

        "EventCode": "0XB7",

        "EventName": "OCR.UC_RD.L3_MISS",

        "MSRIndex": "0x1a6,0x1a7",

        "MSRValue": "0x102184000000",

        "Offcore": "1",

        "SampleAfterValue": "100003",

        "UMask": "0x1"

    },

    {

        "BriefDescription": "Counts uncached memory reads that were not supplied by the L3 cache.",

        "Counter": "0,1,2,3",

        "EventCode": "0XB7",

        "EventName": "OCR.UC_RD.L3_MISS_LOCAL",

        "MSRIndex": "0x1a6,0x1a7",

        "MSRValue": "0x102184000000",

        "Offcore": "1",

        "SampleAfterValue": "100003",

        "UMask": "0x1"

    },

    {

        "BriefDescription": "Counts uncached memory writes that were not supplied by the L3 cache.",

        "Counter": "0,1,2,3",

        "EventCode": "0XB7",

        "EventName": "OCR.UC_WR.L3_MISS",

        "MSRIndex": "0x1a6,0x1a7",

        "MSRValue": "0x202184000000",

        "Offcore": "1",

        "SampleAfterValue": "100003",

        "UMask": "0x1"

    },

    {

        "BriefDescription": "Counts uncached memory writes that were not supplied by the L3 cache.",

        "Counter": "0,1,2,3",

        "EventCode": "0XB7",

        "EventName": "OCR.UC_WR.L3_MISS_LOCAL",

        "MSRIndex": "0x1a6,0x1a7",

        "MSRValue": "0x202184000000",

        "Offcore": "1",

        "SampleAfterValue": "100003",

        "UMask": "0x1"

    }

tools/perf/pmu-events/arch/x86/snowridgex/other.json

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