Commit 9b3938c0 authored by Xingyu Wu's avatar Xingyu Wu Committed by Conor Dooley
Browse files

dt-bindings: clock: Add StarFive JH7110 Image-Signal-Process clock and reset generator 



Add bindings for the Image-Signal-Process clock and reset
generator (ISPCRG) on the JH7110 RISC-V SoC by StarFive Ltd.

Acked-by: default avatarPalmer Dabbelt <palmer@rivosinc.com>
Reviewed-by: default avatarEmil Renner Berthing <emil.renner.berthing@canonical.com>
Reviewed-by: default avatarKrzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: default avatarXingyu Wu <xingyu.wu@starfivetech.com>
Signed-off-by: default avatarConor Dooley <conor.dooley@microchip.com>
parent 14b14a57

Documentation/devicetree/bindings/clock/starfive,jh7110-ispcrg.yaml

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# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause

%YAML 1.2

---

$id: http://devicetree.org/schemas/clock/starfive,jh7110-ispcrg.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: StarFive JH7110 Image-Signal-Process Clock and Reset Generator



maintainers:

  - Xingyu Wu <xingyu.wu@starfivetech.com>



properties:

  compatible:

    const: starfive,jh7110-ispcrg



  reg:

    maxItems: 1



  clocks:

    items:

      - description: ISP Top core

      - description: ISP Top Axi

      - description: NOC ISP Bus

      - description: external DVP



  clock-names:

    items:

      - const: isp_top_core

      - const: isp_top_axi

      - const: noc_bus_isp_axi

      - const: dvp_clk



  resets:

    items:

      - description: ISP Top core

      - description: ISP Top Axi

      - description: NOC ISP Bus



  '#clock-cells':

    const: 1

    description:

      See <dt-bindings/clock/starfive,jh7110-crg.h> for valid indices.



  '#reset-cells':

    const: 1

    description:

      See <dt-bindings/reset/starfive,jh7110-crg.h> for valid indices.



  power-domains:

    maxItems: 1

    description:

      ISP domain power



required:

  - compatible

  - reg

  - clocks

  - clock-names

  - resets

  - '#clock-cells'

  - '#reset-cells'

  - power-domains



additionalProperties: false



examples:

  - |

    #include <dt-bindings/clock/starfive,jh7110-crg.h>

    #include <dt-bindings/power/starfive,jh7110-pmu.h>

    #include <dt-bindings/reset/starfive,jh7110-crg.h>



    ispcrg: clock-controller@19810000 {

        compatible = "starfive,jh7110-ispcrg";

        reg = <0x19810000 0x10000>;

        clocks = <&syscrg JH7110_SYSCLK_ISP_TOP_CORE>,

                 <&syscrg JH7110_SYSCLK_ISP_TOP_AXI>,

                 <&syscrg JH7110_SYSCLK_NOC_BUS_ISP_AXI>,

                 <&dvp_clk>;

        clock-names = "isp_top_core", "isp_top_axi",

                      "noc_bus_isp_axi", "dvp_clk";

        resets = <&syscrg JH7110_SYSRST_ISP_TOP>,

                 <&syscrg JH7110_SYSRST_ISP_TOP_AXI>,

                 <&syscrg JH7110_SYSRST_NOC_BUS_ISP_AXI>;

        #clock-cells = <1>;

        #reset-cells = <1>;

        power-domains = <&pwrc JH7110_PD_ISP>;

    };

include/dt-bindings/clock/starfive,jh7110-crg.h

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#define JH7110_STGCLK_END			29



/* ISPCRG clocks */

#define JH7110_ISPCLK_DOM4_APB_FUNC		0

#define JH7110_ISPCLK_MIPI_RX0_PXL		1

#define JH7110_ISPCLK_DVP_INV			2

#define JH7110_ISPCLK_M31DPHY_CFG_IN		3

#define JH7110_ISPCLK_M31DPHY_REF_IN		4

#define JH7110_ISPCLK_M31DPHY_TX_ESC_LAN0	5

#define JH7110_ISPCLK_VIN_APB			6

#define JH7110_ISPCLK_VIN_SYS			7

#define JH7110_ISPCLK_VIN_PIXEL_IF0		8

#define JH7110_ISPCLK_VIN_PIXEL_IF1		9

#define JH7110_ISPCLK_VIN_PIXEL_IF2		10

#define JH7110_ISPCLK_VIN_PIXEL_IF3		11

#define JH7110_ISPCLK_VIN_P_AXI_WR		12

#define JH7110_ISPCLK_ISPV2_TOP_WRAPPER_C	13



#define JH7110_ISPCLK_END			14



#endif /* __DT_BINDINGS_CLOCK_STARFIVE_JH7110_CRG_H__ */

include/dt-bindings/reset/starfive,jh7110-crg.h

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#define JH7110_STGRST_END			23



/* ISPCRG resets */

#define JH7110_ISPRST_ISPV2_TOP_WRAPPER_P	0

#define JH7110_ISPRST_ISPV2_TOP_WRAPPER_C	1

#define JH7110_ISPRST_M31DPHY_HW		2

#define JH7110_ISPRST_M31DPHY_B09_AON		3

#define JH7110_ISPRST_VIN_APB			4

#define JH7110_ISPRST_VIN_PIXEL_IF0		5

#define JH7110_ISPRST_VIN_PIXEL_IF1		6

#define JH7110_ISPRST_VIN_PIXEL_IF2		7

#define JH7110_ISPRST_VIN_PIXEL_IF3		8

#define JH7110_ISPRST_VIN_SYS			9

#define JH7110_ISPRST_VIN_P_AXI_RD		10

#define JH7110_ISPRST_VIN_P_AXI_WR		11



#define JH7110_ISPRST_END			12



#endif /* __DT_BINDINGS_RESET_STARFIVE_JH7110_CRG_H__ */