Commit 9abdd497 authored by Mikko Perttunen's avatar Mikko Perttunen Committed by Thierry Reding
Browse files

gpu: host1x: Tegra234 device data and headers 



Add device data and chip headers for Tegra234.

Signed-off-by: default avatarMikko Perttunen <mperttunen@nvidia.com>
Signed-off-by: default avatarThierry Reding <treding@nvidia.com>
parent 7afd1194

drivers/gpu/host1x/Makefile

+2 −1
Original line number Original line Diff line number Diff line
@@ -15,7 +15,8 @@ host1x-y = \ 
	hw/host1x04.o \

	hw/host1x04.o \

	hw/host1x05.o \

	hw/host1x05.o \

	hw/host1x06.o \

	hw/host1x06.o \

	hw/host1x07.o

	hw/host1x07.o \

	hw/host1x08.o





host1x-$(CONFIG_IOMMU_API) += \

host1x-$(CONFIG_IOMMU_API) += \

	context.o

	context.o

drivers/gpu/host1x/dev.c

+42 −0
Original line number Original line Diff line number Diff line
@@ -39,6 +39,7 @@ 
#include "hw/host1x05.h"

#include "hw/host1x05.h"

#include "hw/host1x06.h"

#include "hw/host1x06.h"

#include "hw/host1x07.h"

#include "hw/host1x07.h"

#include "hw/host1x08.h"





void host1x_common_writel(struct host1x *host1x, u32 v, u32 r)

void host1x_common_writel(struct host1x *host1x, u32 v, u32 r)

{

{
@@ -205,7 +206,48 @@ static const struct host1x_info host1x07_info = { 
	.reserve_vblank_syncpts = false,

	.reserve_vblank_syncpts = false,

};

};





/*

 * Tegra234 has two stream ID protection tables, one for setting stream IDs

 * through the channel path via SETSTREAMID, and one for setting them via

 * MMIO. We program each engine's data stream ID in the channel path table

 * and firmware stream ID in the MMIO path table.

 */

static const struct host1x_sid_entry tegra234_sid_table[] = {

	{

		/* VIC channel */

		.base = 0x17b8,

		.offset = 0x30,

		.limit = 0x30

	},

	{

		/* VIC MMIO */

		.base = 0x1688,

		.offset = 0x34,

		.limit = 0x34

	},

};



static const struct host1x_info host1x08_info = {

	.nb_channels = 63,

	.nb_pts = 1024,

	.nb_mlocks = 24,

	.nb_bases = 0,

	.init = host1x08_init,

	.sync_offset = 0x0,

	.dma_mask = DMA_BIT_MASK(40),

	.has_wide_gather = true,

	.has_hypervisor = true,

	.has_common = true,

	.num_sid_entries = ARRAY_SIZE(tegra234_sid_table),

	.sid_table = tegra234_sid_table,

	.streamid_vm_table = { 0x1004, 128 },

	.classid_vm_table = { 0x1404, 25 },

	.mmio_vm_table = { 0x1504, 25 },

	.reserve_vblank_syncpts = false,

};



static const struct of_device_id host1x_of_match[] = {

static const struct of_device_id host1x_of_match[] = {

	{ .compatible = "nvidia,tegra234-host1x", .data = &host1x08_info, },

	{ .compatible = "nvidia,tegra194-host1x", .data = &host1x07_info, },

	{ .compatible = "nvidia,tegra194-host1x", .data = &host1x07_info, },

	{ .compatible = "nvidia,tegra186-host1x", .data = &host1x06_info, },

	{ .compatible = "nvidia,tegra186-host1x", .data = &host1x06_info, },

	{ .compatible = "nvidia,tegra210-host1x", .data = &host1x05_info, },

	{ .compatible = "nvidia,tegra210-host1x", .data = &host1x05_info, },

drivers/gpu/host1x/hw/host1x08.c

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// SPDX-License-Identifier: GPL-2.0-only

/*

 * Host1x init for Tegra234 SoCs

 *

 * Copyright (c) 2022 NVIDIA Corporation.

 */



/* include hw specification */

#include "host1x08.h"

#include "host1x08_hardware.h"



/* include code */

#define HOST1X_HW 8



#include "cdma_hw.c"

#include "channel_hw.c"

#include "debug_hw.c"

#include "intr_hw.c"

#include "syncpt_hw.c"



#include "../dev.h"



int host1x08_init(struct host1x *host)

{

	host->channel_op = &host1x_channel_ops;

	host->cdma_op = &host1x_cdma_ops;

	host->cdma_pb_op = &host1x_pushbuffer_ops;

	host->syncpt_op = &host1x_syncpt_ops;

	host->intr_op = &host1x_intr_ops;

	host->debug_op = &host1x_debug_ops;



	return 0;

}

drivers/gpu/host1x/hw/host1x08.h

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/* SPDX-License-Identifier: GPL-2.0-only */

/*

 * Host1x init for Tegra234 SoCs

 *

 * Copyright (c) 2018 NVIDIA Corporation.

 */



#ifndef HOST1X_HOST1X08_H

#define HOST1X_HOST1X08_H



struct host1x;



int host1x08_init(struct host1x *host);



#endif

drivers/gpu/host1x/hw/host1x08_hardware.h

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+21 −0
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/* SPDX-License-Identifier: GPL-2.0-only */

/*

 * Tegra host1x Register Offsets for Tegra234

 *

 * Copyright (c) 2022 NVIDIA Corporation.

 */



#ifndef __HOST1X_HOST1X08_HARDWARE_H

#define __HOST1X_HOST1X08_HARDWARE_H



#include <linux/types.h>

#include <linux/bitops.h>



#include "hw_host1x08_uclass.h"

#include "hw_host1x08_vm.h"

#include "hw_host1x08_hypervisor.h"

#include "hw_host1x08_common.h"



#include "opcodes.h"



#endif