Commit 9ab29e15 authored by Jani Nikula's avatar Jani Nikula
Browse files

drm/i915/dp: read sink UHBR rates 



See if sink supports DP 2.0 128b/132b channel encoding, and update sink
rates accordingly.

FIXME: Also take LTTPR 128b/132b into account.

v2: Add build-time check for ->sink_rates size (Ville)

Reviewed-by: default avatarManasi Navare <manasi.d.navare@intel.com>
Reviewed-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: default avatarJani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/089d807e887d308c52c84cf58dfb6777de18872d.1629735412.git.jani.nikula@intel.com
parent f5b21c2e

drivers/gpu/drm/i915/display/intel_dp.c

+20 −0
Original line number Diff line number Diff line
@@ -141,6 +141,26 @@ static void intel_dp_set_sink_rates(struct intel_dp *intel_dp) 
		intel_dp->sink_rates[i] = dp_rates[i];

	}



	/*

	 * Sink rates for 128b/132b. If set, sink should support all 8b/10b

	 * rates and 10 Gbps.

	 */

	if (intel_dp->dpcd[DP_MAIN_LINK_CHANNEL_CODING] & DP_CAP_ANSI_128B132B) {

		u8 uhbr_rates = 0;



		BUILD_BUG_ON(ARRAY_SIZE(intel_dp->sink_rates) < ARRAY_SIZE(dp_rates) + 3);



		drm_dp_dpcd_readb(&intel_dp->aux,

				  DP_128B132B_SUPPORTED_LINK_RATES, &uhbr_rates);



		if (uhbr_rates & DP_UHBR10)

			intel_dp->sink_rates[i++] = 1000000;

		if (uhbr_rates & DP_UHBR13_5)

			intel_dp->sink_rates[i++] = 1350000;

		if (uhbr_rates & DP_UHBR20)

			intel_dp->sink_rates[i++] = 2000000;

	}



	intel_dp->num_sink_rates = i;

}