Commit 9a890510 authored by Chengci.Xu's avatar Chengci.Xu Committed by Joerg Roedel
Browse files

iommu/mediatek: Adjust mtk_iommu_config flow 



If there are many ports in a infra master, current flow will update
the INFRA register many times. This patch saves all ports to portid_msk
in the front of mtk_iommu_config(), then update only once for the IOMMU
configure. After this, we could avoid send too many SMC calls to ATF in
MT8188.

Prepare for MT8188, also reduce the indention without functional change.

Signed-off-by: default avatarChengci.Xu <chengci.xu@mediatek.com>
Signed-off-by: default avatarYong Wu <yong.wu@mediatek.com>
Reviewed-by: default avatarAngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: default avatarAlexandre Mergnat <amergnat@baylibre.com>
Link: https://lore.kernel.org/r/20230602090227.7264-4-yong.wu@mediatek.com


Signed-off-by: default avatarJoerg Roedel <jroedel@suse.de>
parent cf69ef46

drivers/iommu/mtk_iommu.c

+32 −26
Original line number Diff line number Diff line
@@ -579,41 +579,47 @@ static int mtk_iommu_config(struct mtk_iommu_data *data, struct device *dev, 
	unsigned int                 larbid, portid;

	struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev);

	const struct mtk_iommu_iova_region *region;

	u32 peri_mmuen, peri_mmuen_msk;

	unsigned long portid_msk = 0;

	int i, ret = 0;



	for (i = 0; i < fwspec->num_ids; ++i) {

		larbid = MTK_M4U_TO_LARB(fwspec->ids[i]);

		portid = MTK_M4U_TO_PORT(fwspec->ids[i]);

		portid_msk |= BIT(portid);

	}



	if (MTK_IOMMU_IS_TYPE(data->plat_data, MTK_IOMMU_TYPE_MM)) {

		/* All ports should be in the same larb. just use 0 here */

		larbid = MTK_M4U_TO_LARB(fwspec->ids[0]);

		larb_mmu = &data->larb_imu[larbid];



		region = data->plat_data->iova_region + regionid;



		for_each_set_bit(portid, &portid_msk, 32)

			larb_mmu->bank[portid] = upper_32_bits(region->iova_base);



			dev_dbg(dev, "%s iommu for larb(%s) port %d region %d rgn-bank %d.\n",

		dev_dbg(dev, "%s iommu for larb(%s) port 0x%lx region %d rgn-bank %d.\n",

			enable ? "enable" : "disable", dev_name(larb_mmu->dev),

				portid, regionid, larb_mmu->bank[portid]);

			portid_msk, regionid, upper_32_bits(region->iova_base));



		if (enable)

				larb_mmu->mmu |= MTK_SMI_MMU_EN(portid);

			larb_mmu->mmu |= portid_msk;

		else

				larb_mmu->mmu &= ~MTK_SMI_MMU_EN(portid);

			larb_mmu->mmu &= ~portid_msk;

	} else if (MTK_IOMMU_IS_TYPE(data->plat_data, MTK_IOMMU_TYPE_INFRA)) {

			peri_mmuen_msk = BIT(portid);

		/* PCI dev has only one output id, enable the next writing bit for PCIe */

			if (dev_is_pci(dev))

				peri_mmuen_msk |= BIT(portid + 1);

		if (dev_is_pci(dev)) {

			if (fwspec->num_ids != 1) {

				dev_err(dev, "PCI dev can only have one port.\n");

				return -ENODEV;

			}

			portid_msk |= BIT(portid + 1);

		}



			peri_mmuen = enable ? peri_mmuen_msk : 0;

		ret = regmap_update_bits(data->pericfg, PERICFG_IOMMU_1,

						 peri_mmuen_msk, peri_mmuen);

					 (u32)portid_msk, enable ? (u32)portid_msk : 0);

		if (ret)

				dev_err(dev, "%s iommu(%s) inframaster 0x%x fail(%d).\n",

			dev_err(dev, "%s iommu(%s) inframaster 0x%lx fail(%d).\n",

				enable ? "enable" : "disable",

					dev_name(data->dev), peri_mmuen_msk, ret);

		}

				dev_name(data->dev), portid_msk, ret);

	}

	return ret;

}