Commit 9a7ef6d5 authored by Paul Mundt's avatar Paul Mundt
Browse files

sh: Drop CPU subtype IRQ headers. 



This drops the various IRQ headers that were floating around
and primarily providing hardcoded IRQ definitions for the
various CPU subtypes. This quickly got to be an unmaintainable
mess, made even more evident by the subtle breakage introduced
by the SH-2 and SH-2A changes.

Now that subtypes are able to register IRQ maps directly, just
rip all of the headers out.

Signed-off-by: default avatarPaul Mundt <lethal@linux-sh.org>
parent 417528a2

arch/sh/boards/renesas/r7780rp/irq.c

+1 −0
Original line number Diff line number Diff line
@@ -10,6 +10,7 @@ 
 */

#include <linux/init.h>

#include <linux/irq.h>

#include <linux/interrupt.h>

#include <linux/io.h>

#include <asm/r7780rp.h>

arch/sh/drivers/pci/pci-sh7780.c

+14 −0
Original line number Diff line number Diff line
@@ -22,6 +22,20 @@ 
#include <linux/delay.h>

#include "pci-sh4.h"



#define INTC_BASE	0xffd00000

#define INTC_ICR0	(INTC_BASE+0x0)

#define INTC_ICR1	(INTC_BASE+0x1c)

#define INTC_INTPRI	(INTC_BASE+0x10)

#define INTC_INTREQ	(INTC_BASE+0x24)

#define INTC_INTMSK0	(INTC_BASE+0x44)

#define INTC_INTMSK1	(INTC_BASE+0x48)

#define INTC_INTMSK2	(INTC_BASE+0x40080)

#define INTC_INTMSKCLR0	(INTC_BASE+0x64)

#define INTC_INTMSKCLR1	(INTC_BASE+0x68)

#define INTC_INTMSKCLR2	(INTC_BASE+0x40084)

#define INTC_INT2MSKR	(INTC_BASE+0x40038)

#define INTC_INT2MSKCR	(INTC_BASE+0x4003c)



/*

 * Initialization. Try all known PCI access methods. Note that we support

 * using both PCI BIOS and direct access: in such cases, we use I/O ports

arch/sh/kernel/cpu/irq/intc2.c

+15 −10
Original line number Diff line number Diff line
@@ -11,22 +11,29 @@ 
 * Hitachi 7751, the STM ST40 STB1, SH7760, and SH7780.

 */

#include <linux/kernel.h>

#include <linux/irq.h>

#include <linux/interrupt.h>

#include <linux/io.h>

#include <asm/system.h>



#if defined(CONFIG_CPU_SUBTYPE_SH7760)

#define INTC2_BASE	0xfe080000

#define INTC2_INTMSK	(INTC2_BASE + 0x40)

#define INTC2_INTMSKCLR	(INTC2_BASE + 0x60)

#elif defined(CONFIG_CPU_SUBTYPE_SH7780)

#define INTC2_BASE	0xffd40000

#define INTC2_INTMSK	(INTC2_BASE + 0x38)

#define INTC2_INTMSKCLR	(INTC2_BASE + 0x3c)

#endif



static void disable_intc2_irq(unsigned int irq)

{

	struct intc2_data *p = get_irq_chip_data(irq);

	ctrl_outl(1 << p->msk_shift,

		  INTC2_BASE + INTC2_INTMSK_OFFSET + p->msk_offset);

	ctrl_outl(1 << p->msk_shift, INTC2_INTMSK + p->msk_offset);

}



static void enable_intc2_irq(unsigned int irq)

{

	struct intc2_data *p = get_irq_chip_data(irq);

	ctrl_outl(1 << p->msk_shift,

		  INTC2_BASE + INTC2_INTMSKCLR_OFFSET + p->msk_offset);

	ctrl_outl(1 << p->msk_shift, INTC2_INTMSKCLR + p->msk_offset);

}



static struct irq_chip intc2_irq_chip = {
@@ -61,12 +68,10 @@ void make_intc2_irq(struct intc2_data *table, unsigned int nr_irqs) 
		/* Set the priority level */

		local_irq_save(flags);



		ipr = ctrl_inl(INTC2_BASE + INTC2_INTPRI_OFFSET +

			       p->ipr_offset);

		ipr = ctrl_inl(INTC2_BASE + p->ipr_offset);

		ipr &= ~(0xf << p->ipr_shift);

		ipr |= p->priority << p->ipr_shift;

		ctrl_outl(ipr, INTC2_BASE + INTC2_INTPRI_OFFSET +

			  p->ipr_offset);

		ctrl_outl(ipr, INTC2_BASE + p->ipr_offset);



		local_irq_restore(flags);

arch/sh/kernel/cpu/irq/ipr.c

+2 −4
Original line number Diff line number Diff line
@@ -19,10 +19,8 @@ 
#include <linux/init.h>

#include <linux/irq.h>

#include <linux/module.h>

#include <asm/system.h>

#include <asm/io.h>

#include <asm/machvec.h>



#include <linux/io.h>

#include <linux/interrupt.h>



static void disable_ipr_irq(unsigned int irq)

{

arch/sh/kernel/cpu/sh4/setup-sh7780.c

+19 −17
Original line number Diff line number Diff line
@@ -79,25 +79,27 @@ static int __init sh7780_devices_setup(void) 
__initcall(sh7780_devices_setup);



static struct intc2_data intc2_irq_table[] = {

	{ 28, 0, 24, 0, INTC_TMU0_MSK, 2 },

	{ 21, 1, 0, 0, INTC_RTC_MSK, TIMER_PRIORITY },

	{ 22, 1, 1, 0, INTC_RTC_MSK, TIMER_PRIORITY },

	{ 23, 1, 2, 0, INTC_RTC_MSK, TIMER_PRIORITY },

	{ SCIF0_ERI_IRQ, 8, 24, 0, INTC_SCIF0_MSK, SCIF0_PRIORITY },

	{ SCIF0_RXI_IRQ, 8, 24, 0, INTC_SCIF0_MSK, SCIF0_PRIORITY },

	{ SCIF0_BRI_IRQ, 8, 24, 0, INTC_SCIF0_MSK, SCIF0_PRIORITY },

	{ SCIF0_TXI_IRQ, 8, 24, 0, INTC_SCIF0_MSK, SCIF0_PRIORITY },

	{ 28, 0, 24, 0, 0, 2 },		/* TMU0 */



	{ SCIF1_ERI_IRQ, 8, 16, 0, INTC_SCIF1_MSK, SCIF1_PRIORITY },

	{ SCIF1_RXI_IRQ, 8, 16, 0, INTC_SCIF1_MSK, SCIF1_PRIORITY },

	{ SCIF1_BRI_IRQ, 8, 16, 0, INTC_SCIF1_MSK, SCIF1_PRIORITY },

	{ SCIF1_TXI_IRQ, 8, 16, 0, INTC_SCIF1_MSK, SCIF1_PRIORITY },

	{ 21, 1,  0, 0, 2, 2 },

	{ 22, 1,  1, 0, 2, 2 },

	{ 23, 1,  2, 0, 2, 2 },



	{ PCIC0_IRQ, 0x10,  8, 0, INTC_PCIC0_MSK, PCIC0_PRIORITY },

	{ PCIC1_IRQ, 0x10,  0, 0, INTC_PCIC1_MSK, PCIC1_PRIORITY },

	{ PCIC2_IRQ, 0x14, 24, 0, INTC_PCIC2_MSK, PCIC2_PRIORITY },

	{ PCIC3_IRQ, 0x14, 16, 0, INTC_PCIC3_MSK, PCIC3_PRIORITY },

	{ PCIC4_IRQ, 0x14,  8, 0, INTC_PCIC4_MSK, PCIC4_PRIORITY },

	{ 40, 8, 24, 0, 3, 3 },		/* SCIF0 ERI */

	{ 41, 8, 24, 0, 3, 3 },		/* SCIF0 RXI */

	{ 42, 8, 24, 0, 3, 3 },		/* SCIF0 BRI */

	{ 43, 8, 24, 0, 3, 3 },		/* SCIF0 TXI */



	{ 76, 8, 16, 0, 4, 3 },		/* SCIF1 ERI */

	{ 77, 8, 16, 0, 4, 3 },		/* SCIF1 RXI */

	{ 78, 8, 16, 0, 4, 3 },		/* SCIF1 BRI */

	{ 79, 8, 16, 0, 4, 3 },		/* SCIF1 TXI */



	{ 64, 0x10,  8, 0, 14, 2 },	/* PCIC0 */

	{ 65, 0x10,  0, 0, 15, 2 },	/* PCIC1 */

	{ 66, 0x14, 24, 0, 16, 2 },	/* PCIC2 */

	{ 67, 0x14, 16, 0, 17, 2 },	/* PCIC3 */

	{ 68, 0x14,  8, 0, 18, 2 },	/* PCIC4 */

};



void __init init_IRQ_intc2(void)