Unverified Commit 9a754cea authored by openeuler-ci-bot's avatar openeuler-ci-bot Committed by Gitee
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!13373 acc some patch rounds 

Merge Pull Request from: @xiao_jiang_shui 
 
1、Some private patches are reverted and incorporated into the main version of the patch.
2、The support querying the capability register feature is added.
3、Some bugfixes are added.

issue：https://gitee.com/openeuler/kernel/issues/IB5U3U 
 
Link:https://gitee.com/openeuler/kernel/pulls/13373

 

Reviewed-by: default avatarYang Shen <shenyang39@huawei.com>
Signed-off-by: default avatarZhang Peng <zhangpeng362@huawei.com>
parents 0e56a38e a13c3e12

Documentation/ABI/testing/debugfs-hisi-hpre

+7 −0
Original line number Diff line number Diff line
@@ -184,3 +184,10 @@ Date: Apr 2020 
Contact:	linux-crypto@vger.kernel.org

Description:	Dump the total number of time out requests.

		Available for both PF and VF, and take no other effect on HPRE.



What:           /sys/kernel/debug/hisi_hpre/<bdf>/cap_regs

Date:           Oct 2024

Contact:        linux-crypto@vger.kernel.org

Description:    Dump the values of the qm and hpre capability bit registers and

                support the query of device specifications to facilitate fault locating.

                Available for both PF and VF, and take no other effect on HPRE.

Documentation/ABI/testing/debugfs-hisi-sec

+7 −0
Original line number Diff line number Diff line
@@ -157,3 +157,10 @@ Contact: linux-crypto@vger.kernel.org 
Description:	Dump the total number of completed but marked error requests

		to be received.

		Available for both PF and VF, and take no other effect on SEC.



What:           /sys/kernel/debug/hisi_sec2/<bdf>/cap_regs

Date:           Oct 2024

Contact:        linux-crypto@vger.kernel.org

Description:    Dump the values of the qm and sec capability bit registers and

                support the query of device specifications to facilitate fault locating.

                Available for both PF and VF, and take no other effect on SEC.

Documentation/ABI/testing/debugfs-hisi-zip

+7 −0
Original line number Diff line number Diff line
@@ -158,3 +158,10 @@ Contact: linux-crypto@vger.kernel.org 
Description:	Dump the total number of BD type error requests

		to be received.

		Available for both PF and VF, and take no other effect on ZIP.



What:           /sys/kernel/debug/hisi_zip/<bdf>/cap_regs

Date:           Oct 2024

Contact:        linux-crypto@vger.kernel.org

Description:    Dump the values of the qm and zip capability bit registers and

                support the query of device specifications to facilitate fault locating.

                Available for both PF and VF, and take no other effect on ZIP.

drivers/crypto/hisilicon/debugfs.c

+19 −10
Original line number Diff line number Diff line
@@ -13,6 +13,7 @@ 
#define QM_DFX_COMMON_LEN		0xC3

#define QM_DFX_REGS_LEN			4UL

#define QM_DBG_TMP_BUF_LEN		22

#define QM_XQC_ADDR_MASK		GENMASK(31, 0)

#define CURRENT_FUN_MASK		GENMASK(5, 0)

#define CURRENT_Q_MASK			GENMASK(31, 16)

#define QM_SQE_ADDR_MASK		GENMASK(7, 0)
@@ -167,7 +168,6 @@ static void dump_show(struct hisi_qm *qm, void *info, 
static int qm_sqc_dump(struct hisi_qm *qm, char *s, char *name)

{

	struct device *dev = &qm->pdev->dev;

	struct qm_sqc *sqc_curr;

	struct qm_sqc sqc;

	u32 qp_id;

	int ret;
@@ -183,6 +183,8 @@ static int qm_sqc_dump(struct hisi_qm *qm, char *s, char *name) 


	ret = qm_set_and_get_xqc(qm, QM_MB_CMD_SQC, &sqc, qp_id, 1);

	if (!ret) {

		sqc.base_h = cpu_to_le32(QM_XQC_ADDR_MASK);

		sqc.base_l = cpu_to_le32(QM_XQC_ADDR_MASK);

		dump_show(qm, &sqc, sizeof(struct qm_sqc), name);



		return 0;
@@ -190,9 +192,10 @@ static int qm_sqc_dump(struct hisi_qm *qm, char *s, char *name) 


	down_read(&qm->qps_lock);

	if (qm->sqc) {

		sqc_curr = qm->sqc + qp_id;



		dump_show(qm, sqc_curr, sizeof(*sqc_curr), "SOFT SQC");

		memcpy(&sqc, qm->sqc + qp_id, sizeof(struct qm_sqc));

		sqc.base_h = cpu_to_le32(QM_XQC_ADDR_MASK);

		sqc.base_l = cpu_to_le32(QM_XQC_ADDR_MASK);

		dump_show(qm, &sqc, sizeof(struct qm_sqc), "SOFT SQC");

	}

	up_read(&qm->qps_lock);
@@ -202,7 +205,6 @@ static int qm_sqc_dump(struct hisi_qm *qm, char *s, char *name) 
static int qm_cqc_dump(struct hisi_qm *qm, char *s, char *name)

{

	struct device *dev = &qm->pdev->dev;

	struct qm_cqc *cqc_curr;

	struct qm_cqc cqc;

	u32 qp_id;

	int ret;
@@ -218,6 +220,8 @@ static int qm_cqc_dump(struct hisi_qm *qm, char *s, char *name) 


	ret = qm_set_and_get_xqc(qm, QM_MB_CMD_CQC, &cqc, qp_id, 1);

	if (!ret) {

		cqc.base_h = cpu_to_le32(QM_XQC_ADDR_MASK);

		cqc.base_l = cpu_to_le32(QM_XQC_ADDR_MASK);

		dump_show(qm, &cqc, sizeof(struct qm_cqc), name);



		return 0;
@@ -225,9 +229,10 @@ static int qm_cqc_dump(struct hisi_qm *qm, char *s, char *name) 


	down_read(&qm->qps_lock);

	if (qm->cqc) {

		cqc_curr = qm->cqc + qp_id;



		dump_show(qm, cqc_curr, sizeof(*cqc_curr), "SOFT CQC");

		memcpy(&cqc, qm->cqc + qp_id, sizeof(struct qm_cqc));

		cqc.base_h = cpu_to_le32(QM_XQC_ADDR_MASK);

		cqc.base_l = cpu_to_le32(QM_XQC_ADDR_MASK);

		dump_show(qm, &cqc, sizeof(struct qm_cqc), "SOFT CQC");

	}

	up_read(&qm->qps_lock);
@@ -263,6 +268,10 @@ static int qm_eqc_aeqc_dump(struct hisi_qm *qm, char *s, char *name) 
	if (ret)

		return ret;



	aeqc.base_h = cpu_to_le32(QM_XQC_ADDR_MASK);

	aeqc.base_l = cpu_to_le32(QM_XQC_ADDR_MASK);

	eqc.base_h = cpu_to_le32(QM_XQC_ADDR_MASK);

	eqc.base_l = cpu_to_le32(QM_XQC_ADDR_MASK);

	dump_show(qm, xeqc, size, name);



	return ret;
@@ -310,10 +319,10 @@ static int q_dump_param_parse(struct hisi_qm *qm, char *s, 


static int qm_sq_dump(struct hisi_qm *qm, char *s, char *name)

{

	u16 sq_depth = qm->qp_array->cq_depth;

	void *sqe;

	u16 sq_depth = qm->qp_array->sq_depth;

	struct hisi_qp *qp;

	u32 qp_id, sqe_id;

	void *sqe;

	int ret;



	ret = q_dump_param_parse(qm, s, &sqe_id, &qp_id, sq_depth);

drivers/crypto/hisilicon/hpre/hpre.h

+23 −0
Original line number Diff line number Diff line
@@ -100,6 +100,29 @@ struct hpre_sqe { 
	__le32 rsvd1[_HPRE_SQE_ALIGN_EXT];

};



enum hpre_cap_table_type {

	QM_RAS_NFE_TYPE = 0x0,

	QM_RAS_NFE_RESET,

	QM_RAS_CE_TYPE,

	HPRE_RAS_NFE_TYPE,

	HPRE_RAS_NFE_RESET,

	HPRE_RAS_CE_TYPE,

	HPRE_CORE_INFO,

	HPRE_CORE_EN,

	HPRE_DRV_ALG_BITMAP,

	HPRE_ALG_BITMAP,

	HPRE_CORE1_BITMAP_CAP,

	HPRE_CORE2_BITMAP_CAP,

	HPRE_CORE3_BITMAP_CAP,

	HPRE_CORE4_BITMAP_CAP,

	HPRE_CORE5_BITMAP_CAP,

	HPRE_CORE6_BITMAP_CAP,

	HPRE_CORE7_BITMAP_CAP,

	HPRE_CORE8_BITMAP_CAP,

	HPRE_CORE9_BITMAP_CAP,

	HPRE_CORE10_BITMAP_CAP,

};



struct hisi_qp *hpre_create_qp(u8 type);

int hpre_algs_register(struct hisi_qm *qm);

void hpre_algs_unregister(struct hisi_qm *qm);