Commit 9a48c597 authored by Marc Zyngier's avatar Marc Zyngier
Browse files

Merge branch kvm-arm64/misc-6.4 into kvmarm-master/fixes 



* kvm-arm64/misc-6.4:
  : .
  : Minor changes for 6.4:
  :
  : - Make better use of the bitmap API (bitmap_zero, bitmap_zalloc...)
  :
  : - FP/SVE/SME documentation update, in the hope that this field
  :   becomes clearer...
  :
  : - Add workaround for the usual Apple SEIS brokenness
  :
  : - Random comment fixes
  : .
  KVM: arm64: vgic: Add Apple M2 PRO/MAX cpus to the list of broken SEIS implementations
  KVM: arm64: Clarify host SME state management
  KVM: arm64: Restructure check for SVE support in FP trap handler
  KVM: arm64: Document check for TIF_FOREIGN_FPSTATE
  KVM: arm64: Fix repeated words in comments
  KVM: arm64: Use the bitmap API to allocate bitmaps
  KVM: arm64: Slightly optimize flush_context()

Signed-off-by: default avatarMarc Zyngier <maz@kernel.org>
parents ac9a7868 e910baa9

arch/arm64/include/asm/cputype.h

+8 −0
Original line number Diff line number Diff line
@@ -126,6 +126,10 @@ 
#define APPLE_CPU_PART_M1_FIRESTORM_MAX	0x029

#define APPLE_CPU_PART_M2_BLIZZARD	0x032

#define APPLE_CPU_PART_M2_AVALANCHE	0x033

#define APPLE_CPU_PART_M2_BLIZZARD_PRO	0x034

#define APPLE_CPU_PART_M2_AVALANCHE_PRO	0x035

#define APPLE_CPU_PART_M2_BLIZZARD_MAX	0x038

#define APPLE_CPU_PART_M2_AVALANCHE_MAX	0x039



#define AMPERE_CPU_PART_AMPERE1		0xAC3
@@ -181,6 +185,10 @@ 
#define MIDR_APPLE_M1_FIRESTORM_MAX MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M1_FIRESTORM_MAX)

#define MIDR_APPLE_M2_BLIZZARD MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M2_BLIZZARD)

#define MIDR_APPLE_M2_AVALANCHE MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M2_AVALANCHE)

#define MIDR_APPLE_M2_BLIZZARD_PRO MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M2_BLIZZARD_PRO)

#define MIDR_APPLE_M2_AVALANCHE_PRO MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M2_AVALANCHE_PRO)

#define MIDR_APPLE_M2_BLIZZARD_MAX MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M2_BLIZZARD_MAX)

#define MIDR_APPLE_M2_AVALANCHE_MAX MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M2_AVALANCHE_MAX)

#define MIDR_AMPERE1 MIDR_CPU_MODEL(ARM_CPU_IMP_AMPERE, AMPERE_CPU_PART_AMPERE1)



/* Fujitsu Erratum 010001 affects A64FX 1.0 and 1.1, (v0r0 and v1r0) */

arch/arm64/kvm/fpsimd.c

+17 −9
Original line number Diff line number Diff line
@@ -81,26 +81,34 @@ void kvm_arch_vcpu_load_fp(struct kvm_vcpu *vcpu) 


	fpsimd_kvm_prepare();



	/*

	 * We will check TIF_FOREIGN_FPSTATE just before entering the

	 * guest in kvm_arch_vcpu_ctxflush_fp() and override this to

	 * FP_STATE_FREE if the flag set.

	 */

	vcpu->arch.fp_state = FP_STATE_HOST_OWNED;



	vcpu_clear_flag(vcpu, HOST_SVE_ENABLED);

	if (read_sysreg(cpacr_el1) & CPACR_EL1_ZEN_EL0EN)

		vcpu_set_flag(vcpu, HOST_SVE_ENABLED);



	/*

	 * We don't currently support SME guests but if we leave

	 * things in streaming mode then when the guest starts running

	 * FPSIMD or SVE code it may generate SME traps so as a

	 * special case if we are in streaming mode we force the host

	 * state to be saved now and exit streaming mode so that we

	 * don't have to handle any SME traps for valid guest

	 * operations. Do this for ZA as well for now for simplicity.

	 */

	if (system_supports_sme()) {

		vcpu_clear_flag(vcpu, HOST_SME_ENABLED);

		if (read_sysreg(cpacr_el1) & CPACR_EL1_SMEN_EL0EN)

			vcpu_set_flag(vcpu, HOST_SME_ENABLED);



		/*

		 * If PSTATE.SM is enabled then save any pending FP

		 * state and disable PSTATE.SM. If we leave PSTATE.SM

		 * enabled and the guest does not enable SME via

		 * CPACR_EL1.SMEN then operations that should be valid

		 * may generate SME traps from EL1 to EL1 which we

		 * can't intercept and which would confuse the guest.

		 *

		 * Do the same for PSTATE.ZA in the case where there

		 * is state in the registers which has not already

		 * been saved, this is very unlikely to happen.

		 */

		if (read_sysreg_s(SYS_SVCR) & (SVCR_SM_MASK | SVCR_ZA_MASK)) {

			vcpu->arch.fp_state = FP_STATE_FREE;

			fpsimd_save_and_flush_cpu_state();

arch/arm64/kvm/hyp/include/hyp/switch.h

+10 −2
Original line number Diff line number Diff line
@@ -177,9 +177,17 @@ static bool kvm_hyp_handle_fpsimd(struct kvm_vcpu *vcpu, u64 *exit_code) 
	sve_guest = vcpu_has_sve(vcpu);

	esr_ec = kvm_vcpu_trap_get_class(vcpu);



	/* Don't handle SVE traps for non-SVE vcpus here: */

	if (!sve_guest && esr_ec != ESR_ELx_EC_FP_ASIMD)

	/* Only handle traps the vCPU can support here: */

	switch (esr_ec) {

	case ESR_ELx_EC_FP_ASIMD:

		break;

	case ESR_ELx_EC_SVE:

		if (!sve_guest)

			return false;

		break;

	default:

		return false;

	}



	/* Valid trap.  Switch the context: */

arch/arm64/kvm/inject_fault.c

+1 −1
Original line number Diff line number Diff line
@@ -204,7 +204,7 @@ void kvm_inject_size_fault(struct kvm_vcpu *vcpu) 
	 * Size Fault at level 0, as if exceeding PARange.

	 *

	 * Non-LPAE guests will only get the external abort, as there

	 * is no way to to describe the ASF.

	 * is no way to describe the ASF.

	 */

	if (vcpu_el1_is_32bit(vcpu) &&

	    !(vcpu_read_sys_reg(vcpu, TCR_EL1) & TTBCR_EAE))

arch/arm64/kvm/vgic/vgic-v3.c

+4 −0
Original line number Diff line number Diff line
@@ -616,6 +616,10 @@ static const struct midr_range broken_seis[] = { 
	MIDR_ALL_VERSIONS(MIDR_APPLE_M1_FIRESTORM_MAX),

	MIDR_ALL_VERSIONS(MIDR_APPLE_M2_BLIZZARD),

	MIDR_ALL_VERSIONS(MIDR_APPLE_M2_AVALANCHE),

	MIDR_ALL_VERSIONS(MIDR_APPLE_M2_BLIZZARD_PRO),

	MIDR_ALL_VERSIONS(MIDR_APPLE_M2_AVALANCHE_PRO),

	MIDR_ALL_VERSIONS(MIDR_APPLE_M2_BLIZZARD_MAX),

	MIDR_ALL_VERSIONS(MIDR_APPLE_M2_AVALANCHE_MAX),

	{},

};