Commit 9a3bf287 authored by Peng Ju Zhou's avatar Peng Ju Zhou Committed by Alex Deucher
Browse files

drm/amdgpu: Fixing "Indirect register access for Navi12 sriov" for vega10 



The NV12 and VEGA10 share the same interface W/RREG32_SOC15*,
the callback functions in these macros may not be defined,
so NULL pointer must be checked but not in
macro __WREG32_SOC15_RLC__, fixing the lock of NULL pointer check.

Signed-off-by: default avatarPeng Ju Zhou <PengJu.Zhou@amd.com>
Reviewed-by: default avatarEmily Deng <Emily.Deng@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 312d9253

drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c

+2 −1
Original line number Diff line number Diff line
@@ -790,7 +790,8 @@ static void gfx_v9_0_rlcg_w(struct amdgpu_device *adev, u32 offset, u32 v, u32 f 
static void gfx_v9_0_rlcg_wreg(struct amdgpu_device *adev, u32 offset,

			       u32 v, u32 acc_flags, u32 hwip)

{

	if (amdgpu_sriov_fullaccess(adev)) {

	if ((acc_flags & AMDGPU_REGS_RLC) &&

	    amdgpu_sriov_fullaccess(adev)) {

		gfx_v9_0_rlcg_w(adev, offset, v, acc_flags);



		return;

drivers/gpu/drm/amd/amdgpu/soc15_common.h

+2 −2
Original line number Diff line number Diff line
@@ -28,12 +28,12 @@ 
#define SOC15_REG_OFFSET(ip, inst, reg)	(adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg)



#define __WREG32_SOC15_RLC__(reg, value, flag, hwip) \

	((amdgpu_sriov_runtime(adev) && adev->gfx.rlc.funcs->rlcg_wreg) ? \

	((amdgpu_sriov_vf(adev) && adev->gfx.rlc.funcs && adev->gfx.rlc.funcs->rlcg_wreg) ? \

	 adev->gfx.rlc.funcs->rlcg_wreg(adev, reg, value, flag, hwip) : \

	 WREG32(reg, value))



#define __RREG32_SOC15_RLC__(reg, flag, hwip) \

	((amdgpu_sriov_runtime(adev) && adev->gfx.rlc.funcs->rlcg_rreg) ? \

	((amdgpu_sriov_vf(adev) && adev->gfx.rlc.funcs && adev->gfx.rlc.funcs->rlcg_rreg) ? \

	 adev->gfx.rlc.funcs->rlcg_rreg(adev, reg, flag, hwip) : \

	 RREG32(reg))