Unverified Commit 9a133f7b authored by Geert Uytterhoeven's avatar Geert Uytterhoeven Committed by Mark Brown
Browse files

spi: sh-msiof: Fill in spi_transfer.effective_speed_hz 



Fill in the effective bit rate used for transfers, so the SPI core can
calculate instead of estimate delays.

Restore "reverse Christmas tree" order of local variables while adding
new variables.

Signed-off-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20210113101916.1147695-2-geert+renesas@glider.be


Signed-off-by: default avatarMark Brown <broonie@kernel.org>
parent bfeccc6a

drivers/spi/spi-sh-msiof.c

+7 −3
Original line number Diff line number Diff line
@@ -259,11 +259,13 @@ static const u32 sh_msiof_spi_div_array[] = { 
};



static void sh_msiof_spi_set_clk_regs(struct sh_msiof_spi_priv *p,

				      unsigned long parent_rate, u32 spi_hz)

				      struct spi_transfer *t)

{

	unsigned long parent_rate = clk_get_rate(p->clk);

	unsigned int div_pow = p->min_div_pow;

	u32 spi_hz = t->speed_hz;

	unsigned long div;

	u32 brps, scr;

	unsigned int div_pow = p->min_div_pow;



	if (!spi_hz || !parent_rate) {

		WARN(1, "Invalid clock rate parameters %lu and %u\n",
@@ -292,6 +294,8 @@ static void sh_msiof_spi_set_clk_regs(struct sh_msiof_spi_priv *p, 
		brps = 32;

	}



	t->effective_speed_hz = parent_rate / (brps << div_pow);



	scr = sh_msiof_spi_div_array[div_pow] | SISCR_BRPS(brps);

	sh_msiof_write(p, SITSCR, scr);

	if (!(p->ctlr->flags & SPI_CONTROLLER_MUST_TX))
@@ -923,7 +927,7 @@ static int sh_msiof_transfer_one(struct spi_controller *ctlr, 


	/* setup clocks (clock already enabled in chipselect()) */

	if (!spi_controller_is_slave(p->ctlr))

		sh_msiof_spi_set_clk_regs(p, clk_get_rate(p->clk), t->speed_hz);

		sh_msiof_spi_set_clk_regs(p, t);



	while (ctlr->dma_tx && len > 15) {

		/*