Commit 9a0775c9 authored by Claudiu Beznea's avatar Claudiu Beznea Committed by Nicolas Ferre
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ARM: at91: ddr: fix typo to align with datasheet naming 



Fix typo on UDDRC_PWRCTL.SELFREF_SW bitmask to align with datasheet
naming.

Signed-off-by: default avatarClaudiu Beznea <claudiu.beznea@microchip.com>
Signed-off-by: default avatarNicolas Ferre <nicolas.ferre@microchip.com>
Link: https://lore.kernel.org/r/20220113144900.906370-4-claudiu.beznea@microchip.com
parent 55614e68

arch/arm/mach-at91/pm_suspend.S

+2 −2
Original line number Diff line number Diff line
@@ -159,7 +159,7 @@ sr_ena_1: 


	/* Switch to self-refresh. */

	ldr	tmp1, [r2, #UDDRC_PWRCTL]

	orr	tmp1, tmp1, #UDDRC_PWRCTRL_SELFREF_SW

	orr	tmp1, tmp1, #UDDRC_PWRCTL_SELFREF_SW

	str	tmp1, [r2, #UDDRC_PWRCTL]



sr_ena_2:
@@ -276,7 +276,7 @@ sr_dis_5: 


	/* Trigger self-refresh exit. */

	ldr	tmp1, [r2, #UDDRC_PWRCTL]

	bic	tmp1, tmp1, #UDDRC_PWRCTRL_SELFREF_SW

	bic	tmp1, tmp1, #UDDRC_PWRCTL_SELFREF_SW

	str	tmp1, [r2, #UDDRC_PWRCTL]



sr_dis_6:

include/soc/at91/sama7-ddr.h

+1 −1
Original line number Diff line number Diff line
@@ -53,7 +53,7 @@ 
#define		UDDRC_STAT_OPMODE_MSK		(0x7 << 0)	/* Operating mode mask */



#define UDDRC_PWRCTL				(0x30)		/* UDDRC Low Power Control Register */

#define		UDDRC_PWRCTRL_SELFREF_SW	(1 << 5)	/* Software self-refresh */

#define		UDDRC_PWRCTL_SELFREF_SW		(1 << 5)	/* Software self-refresh */



#define UDDRC_DFIMISC				(0x1B0)		/* UDDRC DFI Miscellaneous Control Register */

#define		UDDRC_DFIMISC_DFI_INIT_COMPLETE_EN (1 << 0)	/* PHY initialization complete enable signal */