Commit 99a7cacc authored by Michael Walle's avatar Michael Walle Committed by Shawn Guo
Browse files

arm64: dts: freescale: fix arm,sp805 compatible string 



According to Documentation/devicetree/bindings/watchdog/arm,sp805.yaml
the compatible is:
  compatible = "arm,sp805", "arm,primecell";

The current compatible string doesn't exist at all. Fix it.

Signed-off-by: default avatarMichael Walle <michael@walle.cc>
Signed-off-by: default avatarShawn Guo <shawnguo@kernel.org>
parent 628550e2

arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi

+8 −8
Original line number Diff line number Diff line
@@ -847,7 +847,7 @@ 
		};



		cluster1_core0_watchdog: wdt@c000000 {

			compatible = "arm,sp805-wdt", "arm,primecell";

			compatible = "arm,sp805", "arm,primecell";

			reg = <0x0 0xc000000 0x0 0x1000>;

			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL

					    QORIQ_CLK_PLL_DIV(16)>,
@@ -857,7 +857,7 @@ 
		};



		cluster1_core1_watchdog: wdt@c010000 {

			compatible = "arm,sp805-wdt", "arm,primecell";

			compatible = "arm,sp805", "arm,primecell";

			reg = <0x0 0xc010000 0x0 0x1000>;

			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL

					    QORIQ_CLK_PLL_DIV(16)>,
@@ -867,7 +867,7 @@ 
		};



		cluster1_core2_watchdog: wdt@c020000 {

			compatible = "arm,sp805-wdt", "arm,primecell";

			compatible = "arm,sp805", "arm,primecell";

			reg = <0x0 0xc020000 0x0 0x1000>;

			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL

					    QORIQ_CLK_PLL_DIV(16)>,
@@ -877,7 +877,7 @@ 
		};



		cluster1_core3_watchdog: wdt@c030000 {

			compatible = "arm,sp805-wdt", "arm,primecell";

			compatible = "arm,sp805", "arm,primecell";

			reg = <0x0 0xc030000 0x0 0x1000>;

			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL

					    QORIQ_CLK_PLL_DIV(16)>,
@@ -887,7 +887,7 @@ 
		};



		cluster2_core0_watchdog: wdt@c100000 {

			compatible = "arm,sp805-wdt", "arm,primecell";

			compatible = "arm,sp805", "arm,primecell";

			reg = <0x0 0xc100000 0x0 0x1000>;

			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL

					    QORIQ_CLK_PLL_DIV(16)>,
@@ -897,7 +897,7 @@ 
		};



		cluster2_core1_watchdog: wdt@c110000 {

			compatible = "arm,sp805-wdt", "arm,primecell";

			compatible = "arm,sp805", "arm,primecell";

			reg = <0x0 0xc110000 0x0 0x1000>;

			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL

					    QORIQ_CLK_PLL_DIV(16)>,
@@ -907,7 +907,7 @@ 
		};



		cluster2_core2_watchdog: wdt@c120000 {

			compatible = "arm,sp805-wdt", "arm,primecell";

			compatible = "arm,sp805", "arm,primecell";

			reg = <0x0 0xc120000 0x0 0x1000>;

			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL

					    QORIQ_CLK_PLL_DIV(16)>,
@@ -917,7 +917,7 @@ 
		};



		cluster2_core3_watchdog: wdt@c130000 {

			compatible = "arm,sp805-wdt", "arm,primecell";

			compatible = "arm,sp805", "arm,primecell";

			reg = <0x0 0xc130000 0x0 0x1000>;

			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL

					    QORIQ_CLK_PLL_DIV(16)>,

arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi

+8 −8
Original line number Diff line number Diff line
@@ -387,7 +387,7 @@ 
		};



		cluster1_core0_watchdog: wdt@c000000 {

			compatible = "arm,sp805-wdt", "arm,primecell";

			compatible = "arm,sp805", "arm,primecell";

			reg = <0x0 0xc000000 0x0 0x1000>;

			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL

					    QORIQ_CLK_PLL_DIV(4)>,
@@ -397,7 +397,7 @@ 
		};



		cluster1_core1_watchdog: wdt@c010000 {

			compatible = "arm,sp805-wdt", "arm,primecell";

			compatible = "arm,sp805", "arm,primecell";

			reg = <0x0 0xc010000 0x0 0x1000>;

			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL

					    QORIQ_CLK_PLL_DIV(4)>,
@@ -407,7 +407,7 @@ 
		};



		cluster2_core0_watchdog: wdt@c100000 {

			compatible = "arm,sp805-wdt", "arm,primecell";

			compatible = "arm,sp805", "arm,primecell";

			reg = <0x0 0xc100000 0x0 0x1000>;

			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL

					    QORIQ_CLK_PLL_DIV(4)>,
@@ -417,7 +417,7 @@ 
		};



		cluster2_core1_watchdog: wdt@c110000 {

			compatible = "arm,sp805-wdt", "arm,primecell";

			compatible = "arm,sp805", "arm,primecell";

			reg = <0x0 0xc110000 0x0 0x1000>;

			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL

					    QORIQ_CLK_PLL_DIV(4)>,
@@ -427,7 +427,7 @@ 
		};



		cluster3_core0_watchdog: wdt@c200000 {

			compatible = "arm,sp805-wdt", "arm,primecell";

			compatible = "arm,sp805", "arm,primecell";

			reg = <0x0 0xc200000 0x0 0x1000>;

			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL

					    QORIQ_CLK_PLL_DIV(4)>,
@@ -437,7 +437,7 @@ 
		};



		cluster3_core1_watchdog: wdt@c210000 {

			compatible = "arm,sp805-wdt", "arm,primecell";

			compatible = "arm,sp805", "arm,primecell";

			reg = <0x0 0xc210000 0x0 0x1000>;

			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL

					    QORIQ_CLK_PLL_DIV(4)>,
@@ -447,7 +447,7 @@ 
		};



		cluster4_core0_watchdog: wdt@c300000 {

			compatible = "arm,sp805-wdt", "arm,primecell";

			compatible = "arm,sp805", "arm,primecell";

			reg = <0x0 0xc300000 0x0 0x1000>;

			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL

					    QORIQ_CLK_PLL_DIV(4)>,
@@ -457,7 +457,7 @@ 
		};



		cluster4_core1_watchdog: wdt@c310000 {

			compatible = "arm,sp805-wdt", "arm,primecell";

			compatible = "arm,sp805", "arm,primecell";

			reg = <0x0 0xc310000 0x0 0x1000>;

			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL

					    QORIQ_CLK_PLL_DIV(4)>,