Commit 99951878 authored by Shiwu Zhang's avatar Shiwu Zhang Committed by Alex Deucher
Browse files

drm/amdgpu: make the WREG32_SOC15_xx macro to support multi GC 



To write regs on different GCDs, use the inst index.

Signed-off-by: default avatarShiwu Zhang <shiwu.zhang@amd.com>
Reviewed-by: default avatarLe Ma <Le.Ma@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 98a54e88

drivers/gpu/drm/amd/amdgpu/soc15_common.h

+6 −6
Original line number Diff line number Diff line
@@ -157,10 +157,10 @@ 
	do {							\

		uint32_t target_reg = adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg;\

		if (amdgpu_sriov_fullaccess(adev)) {    \

			uint32_t r2 = adev->reg_offset[GC_HWIP][0][prefix##SCRATCH_REG1_BASE_IDX] + prefix##SCRATCH_REG2;	\

			uint32_t r3 = adev->reg_offset[GC_HWIP][0][prefix##SCRATCH_REG1_BASE_IDX] + prefix##SCRATCH_REG3;	\

			uint32_t grbm_cntl = adev->reg_offset[GC_HWIP][0][prefix##GRBM_GFX_CNTL_BASE_IDX] + prefix##GRBM_GFX_CNTL;   \

			uint32_t grbm_idx = adev->reg_offset[GC_HWIP][0][prefix##GRBM_GFX_INDEX_BASE_IDX] + prefix##GRBM_GFX_INDEX;   \

			uint32_t r2 = adev->reg_offset[GC_HWIP][inst][prefix##SCRATCH_REG1_BASE_IDX] + prefix##SCRATCH_REG2;	\

			uint32_t r3 = adev->reg_offset[GC_HWIP][inst][prefix##SCRATCH_REG1_BASE_IDX] + prefix##SCRATCH_REG3;	\

			uint32_t grbm_cntl = adev->reg_offset[GC_HWIP][inst][prefix##GRBM_GFX_CNTL_BASE_IDX] + prefix##GRBM_GFX_CNTL;   \

			uint32_t grbm_idx = adev->reg_offset[GC_HWIP][inst][prefix##GRBM_GFX_INDEX_BASE_IDX] + prefix##GRBM_GFX_INDEX;   \

			if (target_reg == grbm_cntl) \

				WREG32(r2, value);	\

			else if (target_reg == grbm_idx) \
@@ -176,13 +176,13 @@ 


#define WREG32_SOC15_RLC(ip, inst, reg, value) \

	do {							\

		uint32_t target_reg = adev->reg_offset[ip##_HWIP][0][reg##_BASE_IDX] + reg;\

		uint32_t target_reg = adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg;\

		__WREG32_SOC15_RLC__(target_reg, value, AMDGPU_REGS_RLC, ip##_HWIP); \

	} while (0)



#define WREG32_SOC15_RLC_EX(prefix, ip, inst, reg, value) \

	do {							\

			uint32_t target_reg = adev->reg_offset[GC_HWIP][0][reg##_BASE_IDX] + reg;\

			uint32_t target_reg = adev->reg_offset[GC_HWIP][inst][reg##_BASE_IDX] + reg;\

			WREG32_RLC_EX(prefix, target_reg, value); \

	} while (0)