Commit 997b99e3 authored by Vidya Sagar's avatar Vidya Sagar Committed by Bjorn Helgaas
Browse files

PCI: tegra194: Find RAS DES PCIe capability offset 

Find RAS DES PCIe capability offset instead of hardcoding the offset
for each controller.

Link: https://lore.kernel.org/r/20220721142052.25971-10-vidyas@nvidia.com


Signed-off-by: default avatarVidya Sagar <vidyas@nvidia.com>
Signed-off-by: default avatarBjorn Helgaas <bhelgaas@google.com>
parent f1ab409d

drivers/pci/controller/dwc/pcie-designware.h

+19 −0
Original line number Diff line number Diff line
@@ -130,6 +130,25 @@ 
#define PCIE_ATU_UNR_UPPER_TARGET	0x18

#define PCIE_ATU_UNR_UPPER_LIMIT	0x20



/*

 * RAS-DES register definitions

 */

#define PCIE_RAS_DES_EVENT_COUNTER_CONTROL	0x8

#define EVENT_COUNTER_ALL_CLEAR		0x3

#define EVENT_COUNTER_ENABLE_ALL	0x7

#define EVENT_COUNTER_ENABLE_SHIFT	2

#define EVENT_COUNTER_EVENT_SEL_MASK	GENMASK(7, 0)

#define EVENT_COUNTER_EVENT_SEL_SHIFT	16

#define EVENT_COUNTER_EVENT_Tx_L0S	0x2

#define EVENT_COUNTER_EVENT_Rx_L0S	0x3

#define EVENT_COUNTER_EVENT_L1		0x5

#define EVENT_COUNTER_EVENT_L1_1	0x7

#define EVENT_COUNTER_EVENT_L1_2	0x8

#define EVENT_COUNTER_GROUP_SEL_SHIFT	24

#define EVENT_COUNTER_GROUP_5		0x5



#define PCIE_RAS_DES_EVENT_COUNTER_DATA		0xc



/*

 * The default address offset between dbi_base and atu_base. Root controller

 * drivers are not required to initialize atu_base if the offset matches this

drivers/pci/controller/dwc/pcie-tegra194.c

+16 −37
Original line number Diff line number Diff line
@@ -170,19 +170,6 @@ 
#define CFG_TIMER_CTRL_MAX_FUNC_NUM_OFF	0x718

#define CFG_TIMER_CTRL_ACK_NAK_SHIFT	(19)



#define EVENT_COUNTER_ALL_CLEAR		0x3

#define EVENT_COUNTER_ENABLE_ALL	0x7

#define EVENT_COUNTER_ENABLE_SHIFT	2

#define EVENT_COUNTER_EVENT_SEL_MASK	GENMASK(7, 0)

#define EVENT_COUNTER_EVENT_SEL_SHIFT	16

#define EVENT_COUNTER_EVENT_Tx_L0S	0x2

#define EVENT_COUNTER_EVENT_Rx_L0S	0x3

#define EVENT_COUNTER_EVENT_L1		0x5

#define EVENT_COUNTER_EVENT_L1_1	0x7

#define EVENT_COUNTER_EVENT_L1_2	0x8

#define EVENT_COUNTER_GROUP_SEL_SHIFT	24

#define EVENT_COUNTER_GROUP_5		0x5



#define N_FTS_VAL					52

#define FTS_VAL						52
@@ -266,6 +253,7 @@ struct tegra_pcie_dw { 
	u32 num_lanes;

	u32 cid;

	u32 cfg_link_cap_l1sub;

	u32 ras_des_cap;

	u32 pcie_cap_base;

	u32 aspm_cmrt;

	u32 aspm_pwr_on_t;
@@ -574,24 +562,6 @@ static struct pci_ops tegra_pci_ops = { 
};



#if defined(CONFIG_PCIEASPM)

static const u32 event_cntr_ctrl_offset[] = {

	0x1d8,

	0x1a8,

	0x1a8,

	0x1a8,

	0x1c4,

	0x1d8

};



static const u32 event_cntr_data_offset[] = {

	0x1dc,

	0x1ac,

	0x1ac,

	0x1ac,

	0x1c8,

	0x1dc

};



static void disable_aspm_l11(struct tegra_pcie_dw *pcie)

{

	u32 val;
@@ -614,13 +584,16 @@ static inline u32 event_counter_prog(struct tegra_pcie_dw *pcie, u32 event) 
{

	u32 val;



	val = dw_pcie_readl_dbi(&pcie->pci, event_cntr_ctrl_offset[pcie->cid]);

	val = dw_pcie_readl_dbi(&pcie->pci, pcie->ras_des_cap +

				PCIE_RAS_DES_EVENT_COUNTER_CONTROL);

	val &= ~(EVENT_COUNTER_EVENT_SEL_MASK << EVENT_COUNTER_EVENT_SEL_SHIFT);

	val |= EVENT_COUNTER_GROUP_5 << EVENT_COUNTER_GROUP_SEL_SHIFT;

	val |= event << EVENT_COUNTER_EVENT_SEL_SHIFT;

	val |= EVENT_COUNTER_ENABLE_ALL << EVENT_COUNTER_ENABLE_SHIFT;

	dw_pcie_writel_dbi(&pcie->pci, event_cntr_ctrl_offset[pcie->cid], val);

	val = dw_pcie_readl_dbi(&pcie->pci, event_cntr_data_offset[pcie->cid]);

	dw_pcie_writel_dbi(&pcie->pci, pcie->ras_des_cap +

			   PCIE_RAS_DES_EVENT_COUNTER_CONTROL, val);

	val = dw_pcie_readl_dbi(&pcie->pci, pcie->ras_des_cap +

				PCIE_RAS_DES_EVENT_COUNTER_DATA);



	return val;

}
@@ -647,13 +620,15 @@ static int aspm_state_cnt(struct seq_file *s, void *data) 
		   event_counter_prog(pcie, EVENT_COUNTER_EVENT_L1_2));



	/* Clear all counters */

	dw_pcie_writel_dbi(&pcie->pci, event_cntr_ctrl_offset[pcie->cid],

	dw_pcie_writel_dbi(&pcie->pci, pcie->ras_des_cap +

			   PCIE_RAS_DES_EVENT_COUNTER_CONTROL,

			   EVENT_COUNTER_ALL_CLEAR);



	/* Re-enable counting */

	val = EVENT_COUNTER_ENABLE_ALL << EVENT_COUNTER_ENABLE_SHIFT;

	val |= EVENT_COUNTER_GROUP_5 << EVENT_COUNTER_GROUP_SEL_SHIFT;

	dw_pcie_writel_dbi(&pcie->pci, event_cntr_ctrl_offset[pcie->cid], val);

	dw_pcie_writel_dbi(&pcie->pci, pcie->ras_des_cap +

			   PCIE_RAS_DES_EVENT_COUNTER_CONTROL, val);



	return 0;

}
@@ -666,10 +641,14 @@ static void init_host_aspm(struct tegra_pcie_dw *pcie) 
	val = dw_pcie_find_ext_capability(pci, PCI_EXT_CAP_ID_L1SS);

	pcie->cfg_link_cap_l1sub = val + PCI_L1SS_CAP;



	pcie->ras_des_cap = dw_pcie_find_ext_capability(&pcie->pci,

							PCI_EXT_CAP_ID_VNDR);



	/* Enable ASPM counters */

	val = EVENT_COUNTER_ENABLE_ALL << EVENT_COUNTER_ENABLE_SHIFT;

	val |= EVENT_COUNTER_GROUP_5 << EVENT_COUNTER_GROUP_SEL_SHIFT;

	dw_pcie_writel_dbi(pci, event_cntr_ctrl_offset[pcie->cid], val);

	dw_pcie_writel_dbi(pci, pcie->ras_des_cap +

			   PCIE_RAS_DES_EVENT_COUNTER_CONTROL, val);



	/* Program T_cmrt and T_pwr_on values */

	val = dw_pcie_readl_dbi(pci, pcie->cfg_link_cap_l1sub);