Unverified Commit 991e0d9d authored by Arnd Bergmann's avatar Arnd Bergmann
Browse files

Merge tag 'imx-fixes-6.5-2' of... 

Merge tag 'imx-fixes-6.5-2' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into arm/fixes

i.MX fixes for 6.5, 2nd round:

- Fix i.MX93 ANATOP 'reg' resource size to avoid overlapping with TMU
  memory area.
- Fix RTC interrupt level on imx6qdl-phytec-mira board.
- Remove LDB endpoint from from the common imx6sx.dtsi as it causes
  regression for boards that has the LCDIF connected directly to
  a parallel display.
- Drop CSI1 PHY reference clock configuration from i.MX8MM/N device tree
  to avoid overclocking.
- Set a proper default tuning step for i.MX6SX and i.MX7D uSDHC to fix
  a tuning failure seen with some SD cards.

* tag 'imx-fixes-6.5-2' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux:
  arm64: dts: imx93: Fix anatop node size
  ARM: dts: imx: Set default tuning step for imx6sx usdhc
  arm64: dts: imx8mm: Drop CSI1 PHY reference clock configuration
  arm64: dts: imx8mn: Drop CSI1 PHY reference clock configuration
  ARM: dts: imx: Set default tuning step for imx7d usdhc
  ARM: dts: imx6: phytec: fix RTC interrupt level
  ARM: dts: imx6sx: Remove LDB endpoint

Link: https://lore.kernel.org/r/20230809100034.GS151430@dragon


Signed-off-by: default avatarArnd Bergmann <arnd@arndb.de>
parents 52a93d39 78e869dd

arch/arm/boot/dts/nxp/imx/imx6qdl-phytec-mira.dtsi

+1 −1
Original line number Diff line number Diff line
@@ -182,7 +182,7 @@ 
		pinctrl-0 = <&pinctrl_rtc_int>;

		reg = <0x68>;

		interrupt-parent = <&gpio7>;

		interrupts = <8 IRQ_TYPE_LEVEL_HIGH>;

		interrupts = <8 IRQ_TYPE_LEVEL_LOW>;

		status = "disabled";

	};

};

arch/arm/boot/dts/nxp/imx/imx6sx.dtsi

+8 −6
Original line number Diff line number Diff line
@@ -863,7 +863,6 @@ 
							reg = <0>;



							ldb_from_lcdif1: endpoint {

								remote-endpoint = <&lcdif1_to_ldb>;

							};

						};
@@ -1010,6 +1009,8 @@ 
					 <&clks IMX6SX_CLK_USDHC1>;

				clock-names = "ipg", "ahb", "per";

				bus-width = <4>;

				fsl,tuning-start-tap = <20>;

				fsl,tuning-step= <2>;

				status = "disabled";

			};
@@ -1022,6 +1023,8 @@ 
					 <&clks IMX6SX_CLK_USDHC2>;

				clock-names = "ipg", "ahb", "per";

				bus-width = <4>;

				fsl,tuning-start-tap = <20>;

				fsl,tuning-step= <2>;

				status = "disabled";

			};
@@ -1034,6 +1037,8 @@ 
					 <&clks IMX6SX_CLK_USDHC3>;

				clock-names = "ipg", "ahb", "per";

				bus-width = <4>;

				fsl,tuning-start-tap = <20>;

				fsl,tuning-step= <2>;

				status = "disabled";

			};
@@ -1309,11 +1314,8 @@ 
					power-domains = <&pd_disp>;

					status = "disabled";



					ports {

					port {

						lcdif1_to_ldb: endpoint {

								remote-endpoint = <&ldb_from_lcdif1>;

							};

						};

					};

				};

arch/arm/boot/dts/nxp/imx/imx7s.dtsi

+6 −0
Original line number Diff line number Diff line
@@ -1184,6 +1184,8 @@ 
					<&clks IMX7D_USDHC1_ROOT_CLK>;

				clock-names = "ipg", "ahb", "per";

				bus-width = <4>;

				fsl,tuning-step = <2>;

				fsl,tuning-start-tap = <20>;

				status = "disabled";

			};
@@ -1196,6 +1198,8 @@ 
					<&clks IMX7D_USDHC2_ROOT_CLK>;

				clock-names = "ipg", "ahb", "per";

				bus-width = <4>;

				fsl,tuning-step = <2>;

				fsl,tuning-start-tap = <20>;

				status = "disabled";

			};
@@ -1208,6 +1212,8 @@ 
					<&clks IMX7D_USDHC3_ROOT_CLK>;

				clock-names = "ipg", "ahb", "per";

				bus-width = <4>;

				fsl,tuning-step = <2>;

				fsl,tuning-start-tap = <20>;

				status = "disabled";

			};

arch/arm64/boot/dts/freescale/imx8mm.dtsi

+3 −4
Original line number Diff line number Diff line
@@ -1221,10 +1221,9 @@ 
				compatible = "fsl,imx8mm-mipi-csi2";

				reg = <0x32e30000 0x1000>;

				interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;

				assigned-clocks = <&clk IMX8MM_CLK_CSI1_CORE>,

						  <&clk IMX8MM_CLK_CSI1_PHY_REF>;

				assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_1000M>,

							  <&clk IMX8MM_SYS_PLL2_1000M>;

				assigned-clocks = <&clk IMX8MM_CLK_CSI1_CORE>;

				assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_1000M>;



				clock-frequency = <333000000>;

				clocks = <&clk IMX8MM_CLK_DISP_APB_ROOT>,

					 <&clk IMX8MM_CLK_CSI1_ROOT>,

arch/arm64/boot/dts/freescale/imx8mn.dtsi

+2 −4
Original line number Diff line number Diff line
@@ -1175,10 +1175,8 @@ 
				compatible = "fsl,imx8mm-mipi-csi2";

				reg = <0x32e30000 0x1000>;

				interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;

				assigned-clocks = <&clk IMX8MN_CLK_CAMERA_PIXEL>,

						  <&clk IMX8MN_CLK_CSI1_PHY_REF>;

				assigned-clock-parents = <&clk IMX8MN_SYS_PLL2_1000M>,

							  <&clk IMX8MN_SYS_PLL2_1000M>;

				assigned-clocks = <&clk IMX8MN_CLK_CAMERA_PIXEL>;

				assigned-clock-parents = <&clk IMX8MN_SYS_PLL2_1000M>;

				assigned-clock-rates = <333000000>;

				clock-frequency = <333000000>;

				clocks = <&clk IMX8MN_CLK_DISP_APB_ROOT>,