Unverified Commit 99199450 authored by Conor Dooley's avatar Conor Dooley Committed by Palmer Dabbelt
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dt-bindings: riscv: add a capacity-dmips-mhz cpu property 



Since commit 03f11f03 ("RISC-V: Parse cpu topology during boot.")
RISC-V has used the generic arch topology code, which provides for
disparate CPU capacities. We never defined a binding to acquire this
information from the DT though, so document the one already used by the
generic arch topology code: "capacity-dmips-mhz".

Signed-off-by: default avatarConor Dooley <conor.dooley@microchip.com>
Reviewed-by: default avatarLey Foon Tan <leyfoon.tan@starfivetech.com>
Acked-by: default avatarRob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20230104180513.1379453-3-conor@kernel.org


Signed-off-by: default avatarPalmer Dabbelt <palmer@rivosinc.com>
parent 7d207831

Documentation/devicetree/bindings/riscv/cpus.yaml

+6 −0
Original line number Diff line number Diff line
@@ -114,6 +114,12 @@ properties: 
      List of phandles to idle state nodes supported

      by this hart (see ./idle-states.yaml).



  capacity-dmips-mhz:

    description:

      u32 value representing CPU capacity (see ../cpu/cpu-capacity.txt) in

      DMIPS/MHz, relative to highest capacity-dmips-mhz

      in the system.



required:

  - riscv,isa

  - interrupt-controller