Commit 991625f3 authored by Peter Zijlstra's avatar Peter Zijlstra
Browse files

x86/ibt: Add IBT feature, MSR and #CP handling 



The bits required to make the hardware go.. Of note is that, provided
the syscall entry points are covered with ENDBR, #CP doesn't need to
be an IST because we'll never hit the syscall gap.

Signed-off-by: default avatarPeter Zijlstra (Intel) <peterz@infradead.org>
Acked-by: default avatarJosh Poimboeuf <jpoimboe@redhat.com>
Link: https://lore.kernel.org/r/20220308154318.582331711@infradead.org
parent 0aec21cf

arch/x86/include/asm/cpu.h

+1 −0
Original line number Diff line number Diff line
@@ -7,6 +7,7 @@ 
#include <linux/topology.h>

#include <linux/nodemask.h>

#include <linux/percpu.h>

#include <asm/ibt.h>



#ifdef CONFIG_SMP

arch/x86/include/asm/cpufeatures.h

+1 −0
Original line number Diff line number Diff line
@@ -390,6 +390,7 @@ 
#define X86_FEATURE_TSXLDTRK		(18*32+16) /* TSX Suspend Load Address Tracking */

#define X86_FEATURE_PCONFIG		(18*32+18) /* Intel PCONFIG */

#define X86_FEATURE_ARCH_LBR		(18*32+19) /* Intel ARCH LBR */

#define X86_FEATURE_IBT			(18*32+20) /* Indirect Branch Tracking */

#define X86_FEATURE_AVX512_FP16		(18*32+23) /* AVX512 FP16 */

#define X86_FEATURE_SPEC_CTRL		(18*32+26) /* "" Speculation Control (IBRS + IBPB) */

#define X86_FEATURE_INTEL_STIBP		(18*32+27) /* "" Single Thread Indirect Branch Predictors */

arch/x86/include/asm/idtentry.h

+5 −0
Original line number Diff line number Diff line
@@ -617,6 +617,11 @@ DECLARE_IDTENTRY_DF(X86_TRAP_DF, exc_double_fault); 
DECLARE_IDTENTRY_RAW_ERRORCODE(X86_TRAP_DF,	xenpv_exc_double_fault);

#endif



/* #CP */

#ifdef CONFIG_X86_KERNEL_IBT

DECLARE_IDTENTRY_ERRORCODE(X86_TRAP_CP,	exc_control_protection);

#endif



/* #VC */

#ifdef CONFIG_AMD_MEM_ENCRYPT

DECLARE_IDTENTRY_VC(X86_TRAP_VC,	exc_vmm_communication);

arch/x86/include/asm/msr-index.h

+19 −1
Original line number Diff line number Diff line
@@ -360,11 +360,29 @@ 
#define MSR_ATOM_CORE_TURBO_RATIOS	0x0000066c

#define MSR_ATOM_CORE_TURBO_VIDS	0x0000066d





#define MSR_CORE_PERF_LIMIT_REASONS	0x00000690

#define MSR_GFX_PERF_LIMIT_REASONS	0x000006B0

#define MSR_RING_PERF_LIMIT_REASONS	0x000006B1



/* Control-flow Enforcement Technology MSRs */

#define MSR_IA32_U_CET			0x000006a0 /* user mode cet */

#define MSR_IA32_S_CET			0x000006a2 /* kernel mode cet */

#define CET_SHSTK_EN			BIT_ULL(0)

#define CET_WRSS_EN			BIT_ULL(1)

#define CET_ENDBR_EN			BIT_ULL(2)

#define CET_LEG_IW_EN			BIT_ULL(3)

#define CET_NO_TRACK_EN			BIT_ULL(4)

#define CET_SUPPRESS_DISABLE		BIT_ULL(5)

#define CET_RESERVED			(BIT_ULL(6) | BIT_ULL(7) | BIT_ULL(8) | BIT_ULL(9))

#define CET_SUPPRESS			BIT_ULL(10)

#define CET_WAIT_ENDBR			BIT_ULL(11)



#define MSR_IA32_PL0_SSP		0x000006a4 /* ring-0 shadow stack pointer */

#define MSR_IA32_PL1_SSP		0x000006a5 /* ring-1 shadow stack pointer */

#define MSR_IA32_PL2_SSP		0x000006a6 /* ring-2 shadow stack pointer */

#define MSR_IA32_PL3_SSP		0x000006a7 /* ring-3 shadow stack pointer */

#define MSR_IA32_INT_SSP_TAB		0x000006a8 /* exception shadow stack table */



/* Hardware P state interface */

#define MSR_PPERF			0x0000064e

#define MSR_PERF_LIMIT_REASONS		0x0000064f

arch/x86/include/asm/traps.h

+2 −0
Original line number Diff line number Diff line
@@ -18,6 +18,8 @@ void __init trap_init(void); 
asmlinkage __visible noinstr struct pt_regs *vc_switch_off_ist(struct pt_regs *eregs);

#endif



extern bool ibt_selftest(void);



#ifdef CONFIG_X86_F00F_BUG

/* For handling the FOOF bug */

void handle_invalid_op(struct pt_regs *regs);