Commit 98ed6159 authored by Ping-Ke Shih's avatar Ping-Ke Shih Committed by Kalle Valo
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rtw89: correct CCA control



EDCCA signal can block transmitting in certain situation, so ignore this
signal and use others to decide transmitting time.

Signed-off-by: default avatarPing-Ke Shih <pkshih@realtek.com>
Signed-off-by: default avatarKalle Valo <kvalo@kernel.org>
Link: https://lore.kernel.org/r/20220506120216.58567-4-pkshih@realtek.com
parent 4b0d341b
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+3 −2
Original line number Diff line number Diff line
@@ -1890,11 +1890,12 @@ static int cca_ctrl_init(struct rtw89_dev *rtwdev, u8 mac_idx)
		B_AX_CTN_CHK_BASIC_NAV | B_AX_CTN_CHK_BTCCA |
		B_AX_CTN_CHK_EDCCA | B_AX_CTN_CHK_CCA_S80 |
		B_AX_CTN_CHK_CCA_S40 | B_AX_CTN_CHK_CCA_S20 |
		B_AX_CTN_CHK_CCA_P20 | B_AX_SIFS_CHK_EDCCA);
		B_AX_CTN_CHK_CCA_P20);
	val &= ~(B_AX_TB_CHK_TX_NAV | B_AX_TB_CHK_CCA_S80 |
		 B_AX_TB_CHK_CCA_S40 | B_AX_TB_CHK_CCA_S20 |
		 B_AX_SIFS_CHK_CCA_S80 | B_AX_SIFS_CHK_CCA_S40 |
		 B_AX_SIFS_CHK_CCA_S20 | B_AX_CTN_CHK_TXNAV);
		 B_AX_SIFS_CHK_CCA_S20 | B_AX_CTN_CHK_TXNAV |
		 B_AX_SIFS_CHK_EDCCA);

	rtw89_write32(rtwdev, reg, val);