Commit 98ebad48 authored by David S. Miller's avatar David S. Miller
Browse files

Merge branch 'sja1110-doc' 



Vladimir Oltean says:

====================
Document the NXP SJA1110 switch as supported

Now that most of the basic work for SJA1110 support has been done in the
sja1105 DSA driver, let's add the missing documentation bits to make it
clear that the driver can be used.
====================

Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parents 89bddde3 75e99470

Documentation/networking/dsa/sja1105.rst

+57 −4
Original line number Diff line number Diff line
@@ -5,7 +5,7 @@ NXP SJA1105 switch driver 
Overview

========



The NXP SJA1105 is a family of 6 devices:

The NXP SJA1105 is a family of 10 SPI-managed automotive switches:



- SJA1105E: First generation, no TTEthernet

- SJA1105T: First generation, TTEthernet
@@ -13,9 +13,11 @@ The NXP SJA1105 is a family of 6 devices: 
- SJA1105Q: Second generation, TTEthernet, no SGMII

- SJA1105R: Second generation, no TTEthernet, SGMII

- SJA1105S: Second generation, TTEthernet, SGMII



These are SPI-managed automotive switches, with all ports being gigabit

capable, and supporting MII/RMII/RGMII and optionally SGMII on one port.

- SJA1110A: Third generation, TTEthernet, SGMII, integrated 100base-T1 and

  100base-TX PHYs

- SJA1110B: Third generation, TTEthernet, SGMII, 100base-T1, 100base-TX

- SJA1110C: Third generation, TTEthernet, SGMII, 100base-T1, 100base-TX

- SJA1110D: Third generation, TTEthernet, SGMII, 100base-T1



Being automotive parts, their configuration interface is geared towards

set-and-forget use, with minimal dynamic interaction at runtime. They
@@ -579,3 +581,54 @@ A board would need to hook up the PHYs connected to the switch to any other 
MDIO bus available to Linux within the system (e.g. to the DSA master's MDIO

bus). Link state management then works by the driver manually keeping in sync

(over SPI commands) the MAC link speed with the settings negotiated by the PHY.



By comparison, the SJA1110 supports an MDIO slave access point over which its

internal 100base-T1 PHYs can be accessed from the host. This is, however, not

used by the driver, instead the internal 100base-T1 and 100base-TX PHYs are

accessed through SPI commands, modeled in Linux as virtual MDIO buses.



The microcontroller attached to the SJA1110 port 0 also has an MDIO controller

operating in master mode, however the driver does not support this either,

since the microcontroller gets disabled when the Linux driver operates.

Discrete PHYs connected to the switch ports should have their MDIO interface

attached to an MDIO controller from the host system and not to the switch,

similar to SJA1105.



Port compatibility matrix

-------------------------



The SJA1105 port compatibility matrix is:



===== ============== ============== ==============

Port   SJA1105E/T     SJA1105P/Q     SJA1105R/S

===== ============== ============== ==============

0      xMII           xMII           xMII

1      xMII           xMII           xMII

2      xMII           xMII           xMII

3      xMII           xMII           xMII

4      xMII           xMII           SGMII

===== ============== ============== ==============





The SJA1110 port compatibility matrix is:



===== ============== ============== ============== ==============

Port   SJA1110A       SJA1110B       SJA1110C       SJA1110D

===== ============== ============== ============== ==============

0      RevMII (uC)    RevMII (uC)    RevMII (uC)    RevMII (uC)

1      100base-TX     100base-TX     100base-TX

       or SGMII                                     SGMII

2      xMII           xMII           xMII           xMII

       or SGMII                                     or SGMII

3      xMII           xMII           xMII

       or SGMII       or SGMII                      SGMII

       or 2500base-X  or 2500base-X                 or 2500base-X

4      SGMII          SGMII          SGMII          SGMII

       or 2500base-X  or 2500base-X  or 2500base-X  or 2500base-X

5      100base-T1     100base-T1     100base-T1     100base-T1

6      100base-T1     100base-T1     100base-T1     100base-T1

7      100base-T1     100base-T1     100base-T1     100base-T1

8      100base-T1     100base-T1     n/a            n/a

9      100base-T1     100base-T1     n/a            n/a

10     100base-T1     n/a            n/a            n/a

===== ============== ============== ============== ==============

drivers/net/dsa/sja1105/Kconfig

+6 −2
Original line number Diff line number Diff line
@@ -7,8 +7,8 @@ tristate "NXP SJA1105 Ethernet switch family support" 
	select PACKING

	select CRC32

	help

	  This is the driver for the NXP SJA1105 automotive Ethernet switch

	  family. These are 5-port devices and are managed over an SPI

	  This is the driver for the NXP SJA1105 (5-port) and SJA1110 (10-port)

	  automotive Ethernet switch family. These are managed over an SPI

	  interface. Probing is handled based on OF bindings and so is the

	  linkage to PHYLINK. The driver supports the following revisions:

	    - SJA1105E (Gen. 1, No TT-Ethernet)
@@ -17,6 +17,10 @@ tristate "NXP SJA1105 Ethernet switch family support" 
	    - SJA1105Q (Gen. 2, No SGMII, TT-Ethernet)

	    - SJA1105R (Gen. 2, SGMII, No TT-Ethernet)

	    - SJA1105S (Gen. 2, SGMII, TT-Ethernet)

	    - SJA1110A (Gen. 3, SGMII, TT-Ethernet, 100base-TX PHY, 10 ports)

	    - SJA1110B (Gen. 3, SGMII, TT-Ethernet, 100base-TX PHY, 9 ports)

	    - SJA1110C (Gen. 3, SGMII, TT-Ethernet, 100base-TX PHY, 7 ports)

	    - SJA1110D (Gen. 3, SGMII, TT-Ethernet, no 100base-TX PHY, 7 ports)



config NET_DSA_SJA1105_PTP

	bool "Support for the PTP clock on the NXP SJA1105 Ethernet switch"