Commit 98e27a5c authored by Jamie Iles's avatar Jamie Iles
Browse files

ARM: picoxcell: don't reserve irq_descs 



All irq_desc's are now dynamically allocated so we don't need to
statically reserve them.

v2:	- select SPARSE_IRQ and set .nr_irqs to NR_IRQS_LEGACY to skip
	ISA and IRQ 0.

Signed-off-by: default avatarJamie Iles <jamie@jamieiles.com>
parent 513c4dd6

arch/arm/Kconfig

+1 −0
Original line number Diff line number Diff line
@@ -650,6 +650,7 @@ config ARCH_PICOXCELL 
	select HAVE_SCHED_CLOCK

	select HAVE_TCM

	select NO_IOPORT

	select SPARSE_IRQ

	select USE_OF

	help

	  This enables support for systems based on the Picochip picoXcell

arch/arm/mach-picoxcell/common.c

+1 −1
Original line number Diff line number Diff line
@@ -45,7 +45,7 @@ static void __init picoxcell_init_irq(void) 


DT_MACHINE_START(PICOXCELL, "Picochip picoXcell")

	.map_io		= picoxcell_map_io,

	.nr_irqs	= ARCH_NR_IRQS,

	.nr_irqs	= NR_IRQS_LEGACY,

	.init_irq	= picoxcell_init_irq,

	.handle_irq	= vic_handle_irq,

	.timer		= &picoxcell_timer,

arch/arm/mach-picoxcell/include/mach/irqs.h

+2 −7
Original line number Diff line number Diff line 
/*

 * Copyright (c) 2011 Picochip Ltd., Jamie Iles

 *

 * This file contains the hardware definitions of the picoXcell SoC devices.

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License as published by

 * the Free Software Foundation; either version 2 of the License, or
@@ -16,10 +14,7 @@ 
#ifndef __MACH_IRQS_H

#define __MACH_IRQS_H



#define ARCH_NR_IRQS			64

#define NR_IRQS				(128 + ARCH_NR_IRQS)



#define IRQ_VIC0_BASE			0

#define IRQ_VIC1_BASE			32

/* We dynamically allocate our irq_desc's. */

#define NR_IRQS				0



#endif /* __MACH_IRQS_H */