Commit 98d771eb authored by Bjorn Helgaas's avatar Bjorn Helgaas
Browse files

Merge branch 'remotes/lorenzo/pci/risc-v' 

- sifive: Add pcie_aux clock to prci driver (Greentime Hu)

- sifive: Use reset-simple in prci driver for PCIe (Greentime Hu)

- Add SiFive FU740 PCIe host controller driver and DT binding (Paul
  Walmsley, Greentime Hu)

* remotes/lorenzo/pci/risc-v:
  riscv: dts: Add PCIe support for the SiFive FU740-C000 SoC
  PCI: fu740: Add SiFive FU740 PCIe host controller driver
  dt-bindings: PCI: Add SiFive FU740 PCIe host controller
  MAINTAINERS: Add maintainers for SiFive FU740 PCIe driver
  clk: sifive: Use reset-simple in prci driver for PCIe driver
  clk: sifive: Add pcie_aux clock in prci driver for PCIe driver
parents 180594f5 ae80d514

Documentation/devicetree/bindings/pci/sifive,fu740-pcie.yaml

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/pci/sifive,fu740-pcie.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: SiFive FU740 PCIe host controller



description: |+

  SiFive FU740 PCIe host controller is based on the Synopsys DesignWare

  PCI core. It shares common features with the PCIe DesignWare core and

  inherits common properties defined in

  Documentation/devicetree/bindings/pci/designware-pcie.txt.



maintainers:

  - Paul Walmsley <paul.walmsley@sifive.com>

  - Greentime Hu <greentime.hu@sifive.com>



allOf:

  - $ref: /schemas/pci/pci-bus.yaml#



properties:

  compatible:

    const: sifive,fu740-pcie



  reg:

    maxItems: 3



  reg-names:

    items:

      - const: dbi

      - const: config

      - const: mgmt



  num-lanes:

    const: 8



  msi-parent: true



  interrupt-names:

    items:

      - const: msi

      - const: inta

      - const: intb

      - const: intc

      - const: intd



  resets:

    description: A phandle to the PCIe power up reset line.

    maxItems: 1



  pwren-gpios:

    description: Should specify the GPIO for controlling the PCI bus device power on.

    maxItems: 1



  reset-gpios:

    maxItems: 1



required:

  - dma-coherent

  - num-lanes

  - interrupts

  - interrupt-names

  - interrupt-parent

  - interrupt-map-mask

  - interrupt-map

  - clock-names

  - clocks

  - resets

  - pwren-gpios

  - reset-gpios



unevaluatedProperties: false



examples:

  - |

    bus {

        #address-cells = <2>;

        #size-cells = <2>;

        #include <dt-bindings/clock/sifive-fu740-prci.h>



        pcie@e00000000 {

            compatible = "sifive,fu740-pcie";

            #address-cells = <3>;

            #size-cells = <2>;

            #interrupt-cells = <1>;

            reg = <0xe 0x00000000 0x0 0x80000000>,

                  <0xd 0xf0000000 0x0 0x10000000>,

                  <0x0 0x100d0000 0x0 0x1000>;

            reg-names = "dbi", "config", "mgmt";

            device_type = "pci";

            dma-coherent;

            bus-range = <0x0 0xff>;

            ranges = <0x81000000  0x0 0x60080000  0x0 0x60080000 0x0 0x10000>,      /* I/O */

                     <0x82000000  0x0 0x60090000  0x0 0x60090000 0x0 0xff70000>,    /* mem */

                     <0x82000000  0x0 0x70000000  0x0 0x70000000 0x0 0x1000000>,    /* mem */

                     <0xc3000000 0x20 0x00000000 0x20 0x00000000 0x20 0x00000000>;  /* mem prefetchable */

            num-lanes = <0x8>;

            interrupts = <56>, <57>, <58>, <59>, <60>, <61>, <62>, <63>, <64>;

            interrupt-names = "msi", "inta", "intb", "intc", "intd";

            interrupt-parent = <&plic0>;

            interrupt-map-mask = <0x0 0x0 0x0 0x7>;

            interrupt-map = <0x0 0x0 0x0 0x1 &plic0 57>,

                            <0x0 0x0 0x0 0x2 &plic0 58>,

                            <0x0 0x0 0x0 0x3 &plic0 59>,

                            <0x0 0x0 0x0 0x4 &plic0 60>;

            clock-names = "pcie_aux";

            clocks = <&prci PRCI_CLK_PCIE_AUX>;

            resets = <&prci 4>;

            pwren-gpios = <&gpio 5 0>;

            reset-gpios = <&gpio 8 0>;

        };

    };

MAINTAINERS

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@@ -13692,6 +13692,14 @@ S: Maintained 
F:	Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt

F:	drivers/pci/controller/dwc/*imx6*









PCI DRIVER FOR FU740









M:	Paul Walmsley <paul.walmsley@sifive.com>









M:	Greentime Hu <greentime.hu@sifive.com>









L:	linux-pci@vger.kernel.org









S:	Maintained









F:	Documentation/devicetree/bindings/pci/sifive,fu740-pcie.yaml









F:	drivers/pci/controller/dwc/pcie-fu740.c

















PCI DRIVER FOR INTEL VOLUME MANAGEMENT DEVICE (VMD)









M:	Jonathan Derrick <jonathan.derrick@intel.com>









L:	linux-pci@vger.kernel.org
































arch/riscv/boot/dts/sifive/fu740-c000.dtsi



+33
−0






























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@@ -159,6 +159,7 @@







			reg = <0x0 0x10000000 0x0 0x1000>;









			clocks = <&hfclk>, <&rtcclk>;









			#clock-cells = <1>;









			#reset-cells = <1>;









		};









		uart0: serial@10010000 {









			compatible = "sifive,fu740-c000-uart", "sifive,uart0";








@@ -289,5 +290,37 @@







			clocks = <&prci PRCI_CLK_PCLK>;









			status = "disabled";









		};









		pcie@e00000000 {









			compatible = "sifive,fu740-pcie";









			#address-cells = <3>;









			#size-cells = <2>;









			#interrupt-cells = <1>;









			reg = <0xe 0x00000000 0x0 0x80000000>,









			      <0xd 0xf0000000 0x0 0x10000000>,









			      <0x0 0x100d0000 0x0 0x1000>;









			reg-names = "dbi", "config", "mgmt";









			device_type = "pci";









			dma-coherent;









			bus-range = <0x0 0xff>;









			ranges = <0x81000000  0x0 0x60080000  0x0 0x60080000 0x0 0x10000>,      /* I/O */









				 <0x82000000  0x0 0x60090000  0x0 0x60090000 0x0 0xff70000>,    /* mem */









				 <0x82000000  0x0 0x70000000  0x0 0x70000000 0x0 0x1000000>,    /* mem */









				 <0xc3000000 0x20 0x00000000 0x20 0x00000000 0x20 0x00000000>;  /* mem prefetchable */









			num-lanes = <0x8>;









			interrupts = <56>, <57>, <58>, <59>, <60>, <61>, <62>, <63>, <64>;









			interrupt-names = "msi", "inta", "intb", "intc", "intd";









			interrupt-parent = <&plic0>;









			interrupt-map-mask = <0x0 0x0 0x0 0x7>;









			interrupt-map = <0x0 0x0 0x0 0x1 &plic0 57>,









					<0x0 0x0 0x0 0x2 &plic0 58>,









					<0x0 0x0 0x0 0x3 &plic0 59>,









					<0x0 0x0 0x0 0x4 &plic0 60>;









			clock-names = "pcie_aux";









			clocks = <&prci PRCI_CLK_PCIE_AUX>;









			pwren-gpios = <&gpio 5 0>;









			reset-gpios = <&gpio 8 0>;









			resets = <&prci 4>;









			status = "okay";









		};









	};









};
























drivers/clk/sifive/Kconfig



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@@ -10,6 +10,8 @@ if CLK_SIFIVE

















config CLK_SIFIVE_PRCI









	bool "PRCI driver for SiFive SoCs"









	select RESET_CONTROLLER









	select RESET_SIMPLE









	select CLK_ANALOGBITS_WRPLL_CLN28HPC









	help









	  Supports the Power Reset Clock interface (PRCI) IP block found in
































drivers/clk/sifive/fu740-prci.c



+11
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@@ -72,6 +72,12 @@ static const struct clk_ops sifive_fu740_prci_hfpclkplldiv_clk_ops = {







	.recalc_rate = sifive_prci_hfpclkplldiv_recalc_rate,









};



















static const struct clk_ops sifive_fu740_prci_pcie_aux_clk_ops = {









	.enable = sifive_prci_pcie_aux_clock_enable,









	.disable = sifive_prci_pcie_aux_clock_disable,









	.is_enabled = sifive_prci_pcie_aux_clock_is_enabled,









};



















/* List of clock controls provided by the PRCI */









struct __prci_clock __prci_init_clocks_fu740[] = {









	[PRCI_CLK_COREPLL] = {








@@ -120,4 +126,9 @@ struct __prci_clock __prci_init_clocks_fu740[] = {







		.parent_name = "hfpclkpll",









		.ops = &sifive_fu740_prci_hfpclkplldiv_clk_ops,









	},









	[PRCI_CLK_PCIE_AUX] = {









		.name = "pcie_aux",









		.parent_name = "hfclk",









		.ops = &sifive_fu740_prci_pcie_aux_clk_ops,









	},









};