Commit 98d006eb authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'perf_urgent_for_v5.14' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip 

Pull perf fixes from Borislav Petkov:

 - Prevent the amd/power module from being removed while in use

 - Mark AMD IBS as not supporting content exclusion

 - Add a workaround for AMD erratum #1197 where IBS registers might not
   be restored properly after exiting CC6 state

 - Fix a potential truncation of a 32-bit variable due to shifting

 - Read the correct bits describing the number of configurable address
   ranges on Intel PT

* tag 'perf_urgent_for_v5.14' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
  perf/x86/amd/power: Assign pmu.module
  perf/x86/amd/ibs: Extend PERF_PMU_CAP_NO_EXCLUDE to IBS Op
  perf/x86/amd/ibs: Work around erratum #1197
  perf/x86/intel/uncore: Fix integer overflow on 23 bit left shift of a u32
  perf/x86/intel/pt: Fix mask of num_address_ranges
parents 072a2767 ccf26483

arch/x86/events/amd/ibs.c

+9 −0
Original line number Diff line number Diff line
@@ -90,6 +90,7 @@ struct perf_ibs { 
	unsigned long			offset_mask[1];

	int				offset_max;

	unsigned int			fetch_count_reset_broken : 1;

	unsigned int			fetch_ignore_if_zero_rip : 1;

	struct cpu_perf_ibs __percpu	*pcpu;



	struct attribute		**format_attrs;
@@ -570,6 +571,7 @@ static struct perf_ibs perf_ibs_op = { 
		.start		= perf_ibs_start,

		.stop		= perf_ibs_stop,

		.read		= perf_ibs_read,

		.capabilities	= PERF_PMU_CAP_NO_EXCLUDE,

	},

	.msr			= MSR_AMD64_IBSOPCTL,

	.config_mask		= IBS_OP_CONFIG_MASK,
@@ -672,6 +674,10 @@ static int perf_ibs_handle_irq(struct perf_ibs *perf_ibs, struct pt_regs *iregs) 
	if (check_rip && (ibs_data.regs[2] & IBS_RIP_INVALID)) {

		regs.flags &= ~PERF_EFLAGS_EXACT;

	} else {

		/* Workaround for erratum #1197 */

		if (perf_ibs->fetch_ignore_if_zero_rip && !(ibs_data.regs[1]))

			goto out;



		set_linear_ip(&regs, ibs_data.regs[1]);

		regs.flags |= PERF_EFLAGS_EXACT;

	}
@@ -769,6 +775,9 @@ static __init void perf_event_ibs_init(void) 
	if (boot_cpu_data.x86 >= 0x16 && boot_cpu_data.x86 <= 0x18)

		perf_ibs_fetch.fetch_count_reset_broken = 1;



	if (boot_cpu_data.x86 == 0x19 && boot_cpu_data.x86_model < 0x10)

		perf_ibs_fetch.fetch_ignore_if_zero_rip = 1;



	perf_ibs_pmu_init(&perf_ibs_fetch, "ibs_fetch");



	if (ibs_caps & IBS_CAPS_OPCNT) {

arch/x86/events/amd/power.c

+1 −0
Original line number Diff line number Diff line
@@ -213,6 +213,7 @@ static struct pmu pmu_class = { 
	.stop		= pmu_event_stop,

	.read		= pmu_event_read,

	.capabilities	= PERF_PMU_CAP_NO_EXCLUDE,

	.module		= THIS_MODULE,

};



static int power_cpu_exit(unsigned int cpu)

arch/x86/events/intel/pt.c

+1 −1
Original line number Diff line number Diff line
@@ -62,7 +62,7 @@ static struct pt_cap_desc { 
	PT_CAP(single_range_output,	0, CPUID_ECX, BIT(2)),

	PT_CAP(output_subsys,		0, CPUID_ECX, BIT(3)),

	PT_CAP(payloads_lip,		0, CPUID_ECX, BIT(31)),

	PT_CAP(num_address_ranges,	1, CPUID_EAX, 0x3),

	PT_CAP(num_address_ranges,	1, CPUID_EAX, 0x7),

	PT_CAP(mtc_periods,		1, CPUID_EAX, 0xffff0000),

	PT_CAP(cycle_thresholds,	1, CPUID_EBX, 0xffff),

	PT_CAP(psb_periods,		1, CPUID_EBX, 0xffff0000),

arch/x86/events/intel/uncore_snbep.c

+1 −1
Original line number Diff line number Diff line
@@ -4811,7 +4811,7 @@ static void __snr_uncore_mmio_init_box(struct intel_uncore_box *box, 
		return;



	pci_read_config_dword(pdev, SNR_IMC_MMIO_BASE_OFFSET, &pci_dword);

	addr = (pci_dword & SNR_IMC_MMIO_BASE_MASK) << 23;

	addr = ((resource_size_t)pci_dword & SNR_IMC_MMIO_BASE_MASK) << 23;



	pci_read_config_dword(pdev, mem_offset, &pci_dword);

	addr |= (pci_dword & SNR_IMC_MMIO_MEM0_MASK) << 12;