Commit 989e4659 authored by Stephen Boyd's avatar Stephen Boyd
Browse files

Merge tag 'clk-imx-6.5' of... 

Merge tag 'clk-imx-6.5' of git://git.kernel.org/pub/scm/linux/kernel/git/abelvesa/linux into clk-imx

Pull i.MX clk driver updates from Abel Vesa:

 - Remove CLK_SET_RATE_PARENT flag from LDB clocks on i.MX6SX
 - Keep UART clocks enabled during kernel boot if earlycon is set
 - Drop the imx_unregister_clocks as there are no users for it
 - Switch to _safe iterator on imx_clk_scu_unregister to avoid use after free
 - Add determine_rate op to the imx8m composite clock
 - Use device managed API for iomap and kzalloc for i.MXRT1050,
   i.MX8MN, i.MX8MP and i.MX93 clock controller drivers
 - Add missing interrupt DT property for the i.MX8M clock controller

* tag 'clk-imx-6.5' of git://git.kernel.org/pub/scm/linux/kernel/git/abelvesa/linux:
  clk: imx: clk-imx8mp: improve error handling in imx8mp_clocks_probe()
  clk: imx93: fix memory leak and missing unwind goto in imx93_clocks_probe
  clk: imx: clk-imx8mn: fix memory leak in imx8mn_clocks_probe
  dt-bindings: clock: imx8m: Add missing interrupt property
  clk: imx: clk-imxrt1050: fix memory leak in imxrt1050_clocks_probe
  clk: imx: composite-8m: Add imx8m_divider_determine_rate
  clk: imx: scu: use _safe list iterator to avoid a use after free
  clk: imx: drop imx_unregister_clocks
  clk: imx6ul: retain early UART clocks during kernel init
  clk: imx: imx6sx: Remove CLK_SET_RATE_PARENT from the LDB clocks
parents ac9a7868 878b02d5

Documentation/devicetree/bindings/clock/imx8m-clock.yaml

+3 −0
Original line number Diff line number Diff line
@@ -24,6 +24,9 @@ properties: 
  reg:

    maxItems: 1



  interrupts:

    maxItems: 2



  clocks:

    minItems: 6

    maxItems: 7

drivers/clk/imx/clk-composite-8m.c

+31 −0
Original line number Diff line number Diff line
@@ -119,10 +119,41 @@ static int imx8m_clk_composite_divider_set_rate(struct clk_hw *hw, 
	return ret;

}



static int imx8m_divider_determine_rate(struct clk_hw *hw,

				      struct clk_rate_request *req)

{

	struct clk_divider *divider = to_clk_divider(hw);

	int prediv_value;

	int div_value;



	/* if read only, just return current value */

	if (divider->flags & CLK_DIVIDER_READ_ONLY) {

		u32 val;



		val = readl(divider->reg);

		prediv_value = val >> divider->shift;

		prediv_value &= clk_div_mask(divider->width);

		prediv_value++;



		div_value = val >> PCG_DIV_SHIFT;

		div_value &= clk_div_mask(PCG_DIV_WIDTH);

		div_value++;



		return divider_ro_determine_rate(hw, req, divider->table,

						 PCG_PREDIV_WIDTH + PCG_DIV_WIDTH,

						 divider->flags, prediv_value * div_value);

	}



	return divider_determine_rate(hw, req, divider->table,

				      PCG_PREDIV_WIDTH + PCG_DIV_WIDTH,

				      divider->flags);

}



static const struct clk_ops imx8m_clk_composite_divider_ops = {

	.recalc_rate = imx8m_clk_composite_divider_recalc_rate,

	.round_rate = imx8m_clk_composite_divider_round_rate,

	.set_rate = imx8m_clk_composite_divider_set_rate,

	.determine_rate = imx8m_divider_determine_rate,

};



static u8 imx8m_clk_composite_mux_get_parent(struct clk_hw *hw)

drivers/clk/imx/clk-imx6sx.c

+4 −4
Original line number Diff line number Diff line
@@ -302,10 +302,10 @@ static void __init imx6sx_clocks_init(struct device_node *ccm_node) 
	hws[IMX6SX_CLK_CKO2_SEL]           = imx_clk_hw_mux("cko2_sel",         base + 0x60,  16,     5,      cko2_sels,         ARRAY_SIZE(cko2_sels));

	hws[IMX6SX_CLK_CKO]                = imx_clk_hw_mux("cko",              base + 0x60,  8,      1,      cko_sels,          ARRAY_SIZE(cko_sels));



	hws[IMX6SX_CLK_LDB_DI1_DIV_SEL]    = imx_clk_hw_mux_flags("ldb_di1_div_sel", base + 0x20, 11, 1, ldb_di1_div_sels, ARRAY_SIZE(ldb_di1_div_sels), CLK_SET_RATE_PARENT);

	hws[IMX6SX_CLK_LDB_DI0_DIV_SEL]    = imx_clk_hw_mux_flags("ldb_di0_div_sel", base + 0x20, 10, 1, ldb_di0_div_sels, ARRAY_SIZE(ldb_di0_div_sels), CLK_SET_RATE_PARENT);

	hws[IMX6SX_CLK_LDB_DI1_SEL]        = imx_clk_hw_mux_flags("ldb_di1_sel",     base + 0x2c, 12, 3, ldb_di1_sels,      ARRAY_SIZE(ldb_di1_sels),    CLK_SET_RATE_PARENT);

	hws[IMX6SX_CLK_LDB_DI0_SEL]        = imx_clk_hw_mux_flags("ldb_di0_sel",     base + 0x2c, 9,  3, ldb_di0_sels,      ARRAY_SIZE(ldb_di0_sels),    CLK_SET_RATE_PARENT);

	hws[IMX6SX_CLK_LDB_DI1_DIV_SEL]    = imx_clk_hw_mux("ldb_di1_div_sel", base + 0x20, 11, 1, ldb_di1_div_sels, ARRAY_SIZE(ldb_di1_div_sels));

	hws[IMX6SX_CLK_LDB_DI0_DIV_SEL]    = imx_clk_hw_mux("ldb_di0_div_sel", base + 0x20, 10, 1, ldb_di0_div_sels, ARRAY_SIZE(ldb_di0_div_sels));

	hws[IMX6SX_CLK_LDB_DI1_SEL]        = imx_clk_hw_mux("ldb_di1_sel",     base + 0x2c, 12, 3, ldb_di1_sels,      ARRAY_SIZE(ldb_di1_sels));

	hws[IMX6SX_CLK_LDB_DI0_SEL]        = imx_clk_hw_mux("ldb_di0_sel",     base + 0x2c, 9,  3, ldb_di0_sels,      ARRAY_SIZE(ldb_di0_sels));

	hws[IMX6SX_CLK_LCDIF1_PRE_SEL]     = imx_clk_hw_mux_flags("lcdif1_pre_sel",  base + 0x38, 15, 3, lcdif1_pre_sels,   ARRAY_SIZE(lcdif1_pre_sels), CLK_SET_RATE_PARENT);

	hws[IMX6SX_CLK_LCDIF1_SEL]         = imx_clk_hw_mux_flags("lcdif1_sel",      base + 0x38, 9,  3, lcdif1_sels,       ARRAY_SIZE(lcdif1_sels),     CLK_SET_RATE_PARENT);

drivers/clk/imx/clk-imx6ul.c

+2 −0
Original line number Diff line number Diff line
@@ -544,6 +544,8 @@ static void __init imx6ul_clocks_init(struct device_node *ccm_node) 


	clk_set_parent(hws[IMX6UL_CLK_ENET1_REF_SEL]->clk, hws[IMX6UL_CLK_ENET_REF]->clk);

	clk_set_parent(hws[IMX6UL_CLK_ENET2_REF_SEL]->clk, hws[IMX6UL_CLK_ENET2_REF]->clk);



	imx_register_uart_clocks();

}



CLK_OF_DECLARE(imx6ul, "fsl,imx6ul-ccm", imx6ul_clocks_init);

drivers/clk/imx/clk-imx8mn.c

+4 −4
Original line number Diff line number Diff line
@@ -323,7 +323,7 @@ static int imx8mn_clocks_probe(struct platform_device *pdev) 
	void __iomem *base;

	int ret;



	clk_hw_data = kzalloc(struct_size(clk_hw_data, hws,

	clk_hw_data = devm_kzalloc(dev, struct_size(clk_hw_data, hws,

					  IMX8MN_CLK_END), GFP_KERNEL);

	if (WARN_ON(!clk_hw_data))

		return -ENOMEM;
@@ -340,10 +340,10 @@ static int imx8mn_clocks_probe(struct platform_device *pdev) 
	hws[IMX8MN_CLK_EXT4] = imx_get_clk_hw_by_name(np, "clk_ext4");



	np = of_find_compatible_node(NULL, NULL, "fsl,imx8mn-anatop");

	base = of_iomap(np, 0);

	base = devm_of_iomap(dev, np, 0, NULL);

	of_node_put(np);

	if (WARN_ON(!base)) {

		ret = -ENOMEM;

	if (WARN_ON(IS_ERR(base))) {

		ret = PTR_ERR(base);

		goto unregister_hws;

	}