Commit 987da486 authored by Yoshihiro Shimoda's avatar Yoshihiro Shimoda Committed by Geert Uytterhoeven
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arm64: dts: renesas: Add Renesas R8A779G0 SoC support 



Add initial support for the Renesas R8A779G0 (R-Car V4H) SoC.

Signed-off-by: default avatarYoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Link: https://lore.kernel.org/r/20220428135058.597586-3-yoshihiro.shimoda.uh@renesas.com


Signed-off-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
parent a4744a1d

arch/arm64/boot/dts/renesas/r8a779g0.dtsi

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+122 −0
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// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

/*

 * Device Tree Source for the R-Car V4H (R8A779G0) SoC

 *

 * Copyright (C) 2022 Renesas Electronics Corp.

 */



#include <dt-bindings/clock/r8a779g0-cpg-mssr.h>

#include <dt-bindings/interrupt-controller/arm-gic.h>

#include <dt-bindings/power/r8a779g0-sysc.h>



/ {

	compatible = "renesas,r8a779g0";

	#address-cells = <2>;

	#size-cells = <2>;



	cpus {

		#address-cells = <1>;

		#size-cells = <0>;



		a76_0: cpu@0 {

			compatible = "arm,cortex-a76";

			reg = <0>;

			device_type = "cpu";

			power-domains = <&sysc R8A779G0_PD_A1E0D0C0>;

		};

	};



	extal_clk: extal {

		compatible = "fixed-clock";

		#clock-cells = <0>;

		/* This value must be overridden by the board */

		clock-frequency = <0>;

	};



	extalr_clk: extalr {

		compatible = "fixed-clock";

		#clock-cells = <0>;

		/* This value must be overridden by the board */

		clock-frequency = <0>;

	};



	pmu_a76 {

		compatible = "arm,cortex-a76-pmu";

		interrupts-extended = <&gic GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;

	};



	/* External SCIF clock - to be overridden by boards that provide it */

	scif_clk: scif {

		compatible = "fixed-clock";

		#clock-cells = <0>;

		clock-frequency = <0>;

	};



	soc: soc {

		compatible = "simple-bus";

		interrupt-parent = <&gic>;

		#address-cells = <2>;

		#size-cells = <2>;

		ranges;



		cpg: clock-controller@e6150000 {

			compatible = "renesas,r8a779g0-cpg-mssr";

			reg = <0 0xe6150000 0 0x4000>;

			clocks = <&extal_clk>, <&extalr_clk>;

			clock-names = "extal", "extalr";

			#clock-cells = <2>;

			#power-domain-cells = <0>;

			#reset-cells = <1>;

		};



		rst: reset-controller@e6160000 {

			compatible = "renesas,r8a779g0-rst";

			reg = <0 0xe6160000 0 0x4000>;

		};



		sysc: system-controller@e6180000 {

			compatible = "renesas,r8a779g0-sysc";

			reg = <0 0xe6180000 0 0x4000>;

			#power-domain-cells = <1>;

		};



		hscif0: serial@e6540000 {

			compatible = "renesas,hscif-r8a779g0",

				     "renesas,rcar-gen4-hscif",

				     "renesas,hscif";

			reg = <0 0xe6540000 0 96>;

			interrupts = <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&cpg CPG_MOD 514>,

				 <&cpg CPG_CORE R8A779G0_CLK_S0D3_PER>,

				 <&scif_clk>;

			clock-names = "fck", "brg_int", "scif_clk";

			power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;

			resets = <&cpg 514>;

			status = "disabled";

		};



		gic: interrupt-controller@f1000000 {

			compatible = "arm,gic-v3";

			#interrupt-cells = <3>;

			#address-cells = <0>;

			interrupt-controller;

			reg = <0x0 0xf1000000 0 0x20000>,

			      <0x0 0xf1060000 0 0x110000>;

			interrupts = <GIC_PPI 9

				      (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>;

		};



		prr: chipid@fff00044 {

			compatible = "renesas,prr";

			reg = <0 0xfff00044 0 4>;

		};

	};



	timer {

		compatible = "arm,armv8-timer";

		interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,

				      <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,

				      <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,

				      <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>;

	};

};