dt-bindings: memory: fsl: convert ifc binding to yaml schema

# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/memory-controllers/fsl/fsl,ifc.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#

title: FSL/NXP Integrated Flash Controller

maintainers:

  - Li Yang <leoyang.li@nxp.com>

description: |

  NXP's integrated flash controller (IFC) is an advanced version of the

  enhanced local bus controller which includes similar programming and signal

  interfaces with an extended feature set. The IFC provides access to multiple

  external memory types, such as NAND flash (SLC and MLC), NOR flash, EPROM,

  SRAM and other memories where address and data are shared on a bus.

properties:

  $nodename:

    pattern: "^memory-controller@[0-9a-f]+$"

  compatible:

    const: fsl,ifc

  "#address-cells":

    enum: [2, 3]

    description: |

      Should be either two or three.  The first cell is the chipselect

      number, and the remaining cells are the offset into the chipselect.

  "#size-cells":

    enum: [1, 2]

    description: |

      Either one or two, depending on how large each chipselect can be.

  reg:

    maxItems: 1

  interrupts:

    minItems: 1

    maxItems: 2

    description: |

      IFC may have one or two interrupts.  If two interrupt specifiers are

      present, the first is the "common" interrupt (CM_EVTER_STAT), and the

      second is the NAND interrupt (NAND_EVTER_STAT).  If there is only one,

      that interrupt reports both types of event.

  little-endian:

    type: boolean

    description: |

      If this property is absent, the big-endian mode will be in use as default

      for registers.

  ranges:

    description: |

      Each range corresponds to a single chipselect, and covers the entire

      access window as configured.

patternProperties:

  "^.*@[a-f0-9]+(,[a-f0-9]+)+$":

    type: object

    description: |

      Child device nodes describe the devices connected to IFC such as NOR (e.g.

      cfi-flash) and NAND (fsl,ifc-nand). There might be board specific devices

      like FPGAs, CPLDs, etc.

    required:

      - compatible

      - reg

required:

  - compatible

  - reg

  - interrupts

additionalProperties: false

examples:

  - |

    soc {

        #address-cells = <2>;

        #size-cells = <2>;

        memory-controller@ffe1e000 {

            compatible = "fsl,ifc";

            #address-cells = <2>;

            #size-cells = <1>;

            reg = <0x0 0xffe1e000 0 0x2000>;

            interrupts = <16 2 19 2>;

            little-endian;

            /* NOR, NAND Flashes and CPLD on board */

            ranges = <0x0 0x0 0x0 0xee000000 0x02000000>,

                     <0x1 0x0 0x0 0xffa00000 0x00010000>,

                     <0x3 0x0 0x0 0xffb00000 0x00020000>;

            flash@0,0 {

                #address-cells = <1>;

                #size-cells = <1>;

                compatible = "cfi-flash";

                reg = <0x0 0x0 0x2000000>;

                bank-width = <2>;

                device-width = <1>;

                partition@0 {

                    /* 32MB for user data */

                    reg = <0x0 0x02000000>;

                    label = "NOR Data";

                };

            };

        };

    };

Integrated Flash Controller

Properties:

- name : Should be ifc

- compatible : should contain "fsl,ifc". The version of the integrated

               flash controller can be found in the IFC_REV register at

               offset zero.

- #address-cells : Should be either two or three.  The first cell is the

                   chipselect number, and the remaining cells are the

                   offset into the chipselect.

- #size-cells : Either one or two, depending on how large each chipselect

                can be.

- reg : Offset and length of the register set for the device

- interrupts: IFC may have one or two interrupts.  If two interrupt

              specifiers are present, the first is the "common"

              interrupt (CM_EVTER_STAT), and the second is the NAND

              interrupt (NAND_EVTER_STAT).  If there is only one,

              that interrupt reports both types of event.

- little-endian : If this property is absent, the big-endian mode will

                  be in use as default for registers.

- ranges : Each range corresponds to a single chipselect, and covers

           the entire access window as configured.

Child device nodes describe the devices connected to IFC such as NOR (e.g.

cfi-flash) and NAND (fsl,ifc-nand). There might be board specific devices

like FPGAs, CPLDs, etc.

Example:

	ifc@ffe1e000 {

		compatible = "fsl,ifc", "simple-bus";

		#address-cells = <2>;

		#size-cells = <1>;

		reg = <0x0 0xffe1e000 0 0x2000>;

		interrupts = <16 2 19 2>;

		little-endian;

		/* NOR, NAND Flashes and CPLD on board */

		ranges = <0x0 0x0 0x0 0xee000000 0x02000000

			  0x1 0x0 0x0 0xffa00000 0x00010000

			  0x3 0x0 0x0 0xffb00000 0x00020000>;

		flash@0,0 {

			#address-cells = <1>;

			#size-cells = <1>;

			compatible = "cfi-flash";

			reg = <0x0 0x0 0x2000000>;

			bank-width = <2>;

			device-width = <1>;

			partition@0 {

				/* 32MB for user data */

				reg = <0x0 0x02000000>;

				label = "NOR Data";

			};

		};

		flash@1,0 {

			#address-cells = <1>;

			#size-cells = <1>;

			compatible = "fsl,ifc-nand";

			reg = <0x1 0x0 0x10000>;

			partition@0 {

				/* This location must not be altered  */

				/* 1MB for u-boot Bootloader Image */

				reg = <0x0 0x00100000>;

				label = "NAND U-Boot Image";

				read-only;

			};

		};

		cpld@3,0 {

			#address-cells = <1>;

			#size-cells = <1>;

			compatible = "fsl,p1010rdb-cpld";

			reg = <0x3 0x0 0x000001f>;

		};

	};