Commit 983bcb4c authored by AMD\ramini's avatar AMD\ramini Committed by Alex Deucher
Browse files

drm/amd/display: Set FixRate bit in VSIF V3 



[Why]
Signal FreeSync display that we are in Fixed Rate mode, and
expand the FreeSync range to 1024.

[How]
Set the new bit in SB16:bit0, and augment the min and max
refresh rate with 2 extra bits.

Signed-off-by: default avatarAMD\ramini <Reza.Amini@amd.com>
Reviewed-by: default avatarAnthony Koo <Anthony.Koo@amd.com>
Acked-by: default avatarEryk Brol <eryk.brol@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 9bc41626

drivers/gpu/drm/amd/display/modules/freesync/freesync.c

+8 −4
Original line number Diff line number Diff line
@@ -610,6 +610,7 @@ static void build_vrr_infopacket_data_v3(const struct mod_vrr_params *vrr, 


	min_programmed = (vrr->state == VRR_STATE_ACTIVE_FIXED) ? fixed_refresh :

			(vrr->state == VRR_STATE_ACTIVE_VARIABLE) ? min_refresh :

			(vrr->state == VRR_STATE_INACTIVE) ? min_refresh :

			max_refresh; // Non-fs case, program nominal range



	max_programmed = (vrr->state == VRR_STATE_ACTIVE_FIXED) ? fixed_refresh :
@@ -622,11 +623,14 @@ static void build_vrr_infopacket_data_v3(const struct mod_vrr_params *vrr, 
	/* PB8 = FreeSync Maximum refresh rate (Hz) */

	infopacket->sb[8] = max_programmed & 0xFF;



	/* PB11 : MSB FreeSync Minimum refresh rate [Hz] - bits 15:8 */

	infopacket->sb[11] = (min_programmed >> 8) & 0xFF;

	/* PB11 : MSB FreeSync Minimum refresh rate [Hz] - bits 9:8 */

	infopacket->sb[11] = (min_programmed >> 8) & 0x03;



	/* PB12 : MSB FreeSync Maximum refresh rate [Hz] - bits 15:8 */

	infopacket->sb[12] = (max_programmed >> 8) & 0xFF;

	/* PB12 : MSB FreeSync Maximum refresh rate [Hz] - bits 9:8 */

	infopacket->sb[12] = (max_programmed >> 8) & 0x03;



	/* PB16 : Reserved bits 7:1, FixedRate bit 0 */

	infopacket->sb[16] = (vrr->state == VRR_STATE_ACTIVE_FIXED) ? 1 : 0;



	//FreeSync HDR

	infopacket->sb[9] = 0;