Commit 9821a195 authored by Seiya Wang's avatar Seiya Wang Committed by Viresh Kumar
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dt-bindings: cpufreq: update cpu type and clock name for MT8173 SoC 



Update the cpu type of cpu2 and cpu3 since MT8173 used Cortex-a72.

Acked-by: default avatarViresh Kumar <viresh.kumar@linaro.org>
Acked-by: default avatarRob Herring <robh@kernel.org>
Reviewed-by: default avatarMatthias Brugger <matthias.bgg@gmail.com>
Signed-off-by: default avatarSeiya Wang <seiya.wang@mediatek.com>
Signed-off-by: default avatarViresh Kumar <viresh.kumar@linaro.org>
parent eed82889

Documentation/devicetree/bindings/cpufreq/cpufreq-mediatek.txt

+4 −4
Original line number Diff line number Diff line
@@ -202,11 +202,11 @@ Example 2 (MT8173 SoC): 


	cpu2: cpu@100 {

		device_type = "cpu";

		compatible = "arm,cortex-a57";

		compatible = "arm,cortex-a72";

		reg = <0x100>;

		enable-method = "psci";

		cpu-idle-states = <&CPU_SLEEP_0>;

		clocks = <&infracfg CLK_INFRA_CA57SEL>,

		clocks = <&infracfg CLK_INFRA_CA72SEL>,

			 <&apmixedsys CLK_APMIXED_MAINPLL>;

		clock-names = "cpu", "intermediate";

		operating-points-v2 = <&cpu_opp_table_b>;
@@ -214,11 +214,11 @@ Example 2 (MT8173 SoC): 


	cpu3: cpu@101 {

		device_type = "cpu";

		compatible = "arm,cortex-a57";

		compatible = "arm,cortex-a72";

		reg = <0x101>;

		enable-method = "psci";

		cpu-idle-states = <&CPU_SLEEP_0>;

		clocks = <&infracfg CLK_INFRA_CA57SEL>,

		clocks = <&infracfg CLK_INFRA_CA72SEL>,

			 <&apmixedsys CLK_APMIXED_MAINPLL>;

		clock-names = "cpu", "intermediate";

		operating-points-v2 = <&cpu_opp_table_b>;