Commit 980bcaf3 authored by Geert Uytterhoeven's avatar Geert Uytterhoeven
Browse files

clk: renesas: rza1: Remove struct rz_cpg 



The register block base pointer as stored in the reg member of the
rz_cpg structure is only used during initialization.  Hence move
it to a local variable, and pass it as a parameter to
rz_cpg_register_clock().

After this, the data member is the only remaining member of the rz_cpg
structure, so the whole structure can be replaced by the data member.

Signed-off-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: default avatarWolfram Sang <wsa+renesas@sang-engineering.com>
Link: https://lore.kernel.org/r/2380285576edaa4ad3dc5eca7e0ca418f068c6ef.1654694831.git.geert+renesas@glider.be
parent 44487798

drivers/clk/renesas/clk-rz.c

+15 −18
Original line number Diff line number Diff line
@@ -15,11 +15,6 @@ 
#include <linux/of_address.h>

#include <linux/slab.h>



struct rz_cpg {

	struct clk_onecell_data data;

	void __iomem *reg;

};



#define CPG_FRQCR	0x10

#define CPG_FRQCR2	0x14
@@ -49,7 +44,8 @@ static u16 __init rz_cpg_read_mode_pins(void) 
}



static struct clk * __init

rz_cpg_register_clock(struct device_node *np, struct rz_cpg *cpg, const char *name)

rz_cpg_register_clock(struct device_node *np, void __iomem *base,

		      const char *name)

{

	u32 val;

	unsigned mult;
@@ -65,7 +61,7 @@ rz_cpg_register_clock(struct device_node *np, struct rz_cpg *cpg, const char *na 
	}



	/* If mapping regs failed, skip non-pll clocks. System will boot anyhow */

	if (!cpg->reg)

	if (!base)

		return ERR_PTR(-ENXIO);



	/* FIXME:"i" and "g" are variable clocks with non-integer dividers (e.g. 2/3)
@@ -73,9 +69,9 @@ rz_cpg_register_clock(struct device_node *np, struct rz_cpg *cpg, const char *na 
	 * let them run at fixed current speed and implement the details later.

	 */

	if (strcmp(name, "i") == 0)

		val = (readl(cpg->reg + CPG_FRQCR) >> 8) & 3;

		val = (readl(base + CPG_FRQCR) >> 8) & 3;

	else if (strcmp(name, "g") == 0)

		val = readl(cpg->reg + CPG_FRQCR2) & 3;

		val = readl(base + CPG_FRQCR2) & 3;

	else

		return ERR_PTR(-EINVAL);
@@ -85,8 +81,9 @@ rz_cpg_register_clock(struct device_node *np, struct rz_cpg *cpg, const char *na 


static void __init rz_cpg_clocks_init(struct device_node *np)

{

	struct rz_cpg *cpg;

	struct clk_onecell_data *data;

	struct clk **clks;

	void __iomem *base;

	unsigned i;

	int num_clks;
@@ -94,14 +91,14 @@ static void __init rz_cpg_clocks_init(struct device_node *np) 
	if (WARN(num_clks <= 0, "can't count CPG clocks\n"))

		return;



	cpg = kzalloc(sizeof(*cpg), GFP_KERNEL);

	data = kzalloc(sizeof(*data), GFP_KERNEL);

	clks = kcalloc(num_clks, sizeof(*clks), GFP_KERNEL);

	BUG_ON(!cpg || !clks);

	BUG_ON(!data || !clks);



	cpg->data.clks = clks;

	cpg->data.clk_num = num_clks;

	data->clks = clks;

	data->clk_num = num_clks;



	cpg->reg = of_iomap(np, 0);

	base = of_iomap(np, 0);



	for (i = 0; i < num_clks; ++i) {

		const char *name;
@@ -109,15 +106,15 @@ static void __init rz_cpg_clocks_init(struct device_node *np) 


		of_property_read_string_index(np, "clock-output-names", i, &name);



		clk = rz_cpg_register_clock(np, cpg, name);

		clk = rz_cpg_register_clock(np, base, name);

		if (IS_ERR(clk))

			pr_err("%s: failed to register %pOFn %s clock (%ld)\n",

			       __func__, np, name, PTR_ERR(clk));

		else

			cpg->data.clks[i] = clk;

			data->clks[i] = clk;

	}



	of_clk_add_provider(np, of_clk_src_onecell_get, &cpg->data);

	of_clk_add_provider(np, of_clk_src_onecell_get, data);



	cpg_mstp_add_clk_domain(np);

}