Commit 97e11307 authored Jul 19, 2021 by Kunkun Jiang Committed by Zheng Zengkai Jul 19, 2021

iommu/arm-smmu-v3: Using HTTU with SMMU STE and stage 2 TTD

virt inclusion
category: feature
bugzilla: https://gitee.com/openeuler/kernel/issues/I401IF


CVE: NA

------------------------------

The SMMU which supports HTTU (Hardware Translation Table Update) can
update the Access flag and the Dirty state bits by hardware. It is
essential to track dirty pages of DMA.

If stage 2 translation is enabled and the SMMU supports HTTU, we set
S2HA (stage 2 Access flag) and S2HD (stage 2 Dirty flag). And set DBM
bit of stage 2 TTD.

Signed-off-by: Kunkun Jiang <jiangkunkun@huawei.com>
Reviewed-by: Keqian Zhu <zhukeqian1@huawei.com>
Signed-off-by: Zheng Zengkai <zhengzengkai@huawei.com>

parent 9b4742a6

drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c

+5 −0

Original line number	Diff line number	Diff line
		@@ -1414,6 +1414,11 @@ static void arm_smmu_write_strtab_ent(struct arm_smmu_master *master, u32 sid,
		STRTAB_STE_2_S2PTW \| STRTAB_STE_2_S2AA64 \|
		STRTAB_STE_2_S2R);

		if (smmu->features & ARM_SMMU_FEAT_HA)
		dst[2] \|= cpu_to_le64(STRTAB_STE_2_S2HA);
		if (smmu->features & ARM_SMMU_FEAT_HD)
		dst[2] \|= cpu_to_le64(STRTAB_STE_2_S2HD);

		dst[3] = cpu_to_le64(vttbr);

		val \|= FIELD_PREP(STRTAB_STE_0_CFG, STRTAB_STE_0_CFG_S2_TRANS);

drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h

+2 −0

Original line number	Diff line number	Diff line
		@@ -262,6 +262,8 @@
		#define STRTAB_STE_2_S2AA64 (1UL << 51)
		#define STRTAB_STE_2_S2ENDI (1UL << 52)
		#define STRTAB_STE_2_S2PTW (1UL << 54)
		#define STRTAB_STE_2_S2HD (1UL << 55)
		#define STRTAB_STE_2_S2HA (1UL << 56)
		#define STRTAB_STE_2_S2R (1UL << 58)

		#define STRTAB_STE_3_S2TTB_MASK GENMASK_ULL(51, 4)

drivers/iommu/io-pgtable-arm.c

+5 −1

Original line number	Diff line number	Diff line
		@@ -400,8 +400,12 @@ static arm_lpae_iopte arm_lpae_prot_to_pte(struct arm_lpae_io_pgtable *data,
		pte = ARM_LPAE_PTE_HAP_FAULT;
		if (prot & IOMMU_READ)
		pte \|= ARM_LPAE_PTE_HAP_READ;
		if (prot & IOMMU_WRITE)
		if (prot & IOMMU_WRITE) {
		pte \|= ARM_LPAE_PTE_HAP_WRITE;
		if (data->iop.fmt == ARM_64_LPAE_S2 &&
		cfg->quirks & IO_PGTABLE_QUIRK_ARM_HD)
		pte \|= ARM_LPAE_PTE_DBM;
		}
		}

		/*