Commit 97d8b136 authored by Chengchang Tang's avatar Chengchang Tang Committed by Juan Zhou
Browse files

RDMA/hns: Replace magic number when fill ADDR to HW 

driver inclusion
category: cleanup
bugzilla: https://gitee.com/openeuler/kernel/issues/I8LY0D



--------------------------------------------------------------------------

This patch repalce magic number in filling ADDR to HW.

Signed-off-by: default avatarChengchang Tang <tangchengchang@huawei.com>
parent 94b41cc2

drivers/infiniband/hw/hns/hns_roce_hw_v2.c

+16 −13
Original line number Diff line number Diff line
@@ -3638,11 +3638,12 @@ static int set_mtpt_pbl(struct hns_roce_dev *hr_dev, 


	/* Aligned to the hardware address access unit */

	for (i = 0; i < count; i++)

		pages[i] >>= 6;

		pages[i] >>= MPT_PBL_BUF_ADDR_S;



	mpt_entry->pbl_size = cpu_to_le32(mr->npages);

	mpt_entry->pbl_ba_l = cpu_to_le32(pbl_ba >> 3);

	hr_reg_write(mpt_entry, MPT_PBL_BA_H, upper_32_bits(pbl_ba >> 3));

	mpt_entry->pbl_ba_l = cpu_to_le32(pbl_ba >> MPT_PBL_BA_ADDR_S);

	hr_reg_write(mpt_entry, MPT_PBL_BA_H,

		     upper_32_bits(pbl_ba >> MPT_PBL_BA_ADDR_S));



	mpt_entry->pa0_l = cpu_to_le32(lower_32_bits(pages[0]));

	hr_reg_write(mpt_entry, MPT_PA0_H, upper_32_bits(pages[0]));
@@ -3769,8 +3770,10 @@ static int hns_roce_v2_frmr_write_mtpt(struct hns_roce_dev *hr_dev, 


	mpt_entry->pbl_size = cpu_to_le32(mr->npages);



	mpt_entry->pbl_ba_l = cpu_to_le32(lower_32_bits(pbl_ba >> 3));

	hr_reg_write(mpt_entry, MPT_PBL_BA_H, upper_32_bits(pbl_ba >> 3));

	mpt_entry->pbl_ba_l = cpu_to_le32(lower_32_bits(

					  pbl_ba >> MPT_PBL_BA_ADDR_S));

	hr_reg_write(mpt_entry, MPT_PBL_BA_H,

		       upper_32_bits(pbl_ba >> MPT_PBL_BA_ADDR_S));



	return 0;

}
@@ -4061,14 +4064,14 @@ static void hns_roce_v2_write_cqc(struct hns_roce_dev *hr_dev, 
		     to_hr_hw_page_shift(hr_cq->mtr.hem_cfg.ba_pg_shift));

	hr_reg_write(cq_context, CQC_CQE_BUF_PG_SZ,

		     to_hr_hw_page_shift(hr_cq->mtr.hem_cfg.buf_pg_shift));

	hr_reg_write(cq_context, CQC_CQE_BA_L, dma_handle >> 3);

	hr_reg_write(cq_context, CQC_CQE_BA_H, (dma_handle >> (32 + 3)));

	hr_reg_write(cq_context, CQC_CQE_BA_L, dma_handle >> CQC_CQE_BA_L_S);

	hr_reg_write(cq_context, CQC_CQE_BA_H, dma_handle >> CQC_CQE_BA_H_S);

	hr_reg_write_bool(cq_context, CQC_DB_RECORD_EN,

			  hr_cq->flags & HNS_ROCE_CQ_FLAG_RECORD_DB);

	hr_reg_write(cq_context, CQC_CQE_DB_RECORD_ADDR_L,

		     ((u32)hr_cq->db.dma) >> 1);

	hr_reg_write(cq_context, CQC_CQE_DB_RECORD_ADDR_H,

		     hr_cq->db.dma >> 32);

		     hr_cq->db.dma >> CQC_CQE_DB_RECORD_ADDR_H_S);

	hr_reg_write(cq_context, CQC_CQ_MAX_CNT,

		     HNS_ROCE_V2_CQ_DEFAULT_BURST_NUM);

	hr_reg_write(cq_context, CQC_CQ_PERIOD,
@@ -5029,11 +5032,11 @@ static int modify_qp_init_to_rtr(struct ib_qp *ibqp, 
		return -EINVAL;

	}



	hr_reg_write(context, QPC_TRRL_BA_L, trrl_ba >> 4);

	hr_reg_write(context, QPC_TRRL_BA_L, trrl_ba >> QPC_TRRL_BA_L_S);

	hr_reg_clear(qpc_mask, QPC_TRRL_BA_L);

	context->trrl_ba = cpu_to_le32(trrl_ba >> (16 + 4));

	context->trrl_ba = cpu_to_le32(trrl_ba >> QPC_TRRL_BA_M_S);

	qpc_mask->trrl_ba = 0;

	hr_reg_write(context, QPC_TRRL_BA_H, trrl_ba >> (32 + 16 + 4));

	hr_reg_write(context, QPC_TRRL_BA_H, trrl_ba >> QPC_TRRL_BA_H_S);

	hr_reg_clear(qpc_mask, QPC_TRRL_BA_H);



	if (hr_dev->pci_dev->revision >= PCI_REVISION_ID_HIP09) {
@@ -5046,9 +5049,9 @@ static int modify_qp_init_to_rtr(struct ib_qp *ibqp, 
		hr_reg_clear(qpc_mask, QPC_V2_IRRL_HEAD);

	}



	context->irrl_ba = cpu_to_le32(irrl_ba >> 6);

	context->irrl_ba = cpu_to_le32(irrl_ba >> QPC_IRRL_BA_L_S);

	qpc_mask->irrl_ba = 0;

	hr_reg_write(context, QPC_IRRL_BA_H, irrl_ba >> (32 + 6));

	hr_reg_write(context, QPC_IRRL_BA_H, irrl_ba >> QPC_IRRL_BA_H_S);

	hr_reg_clear(qpc_mask, QPC_IRRL_BA_H);



	hr_reg_enable(context, QPC_RMT_E2E);

drivers/infiniband/hw/hns/hns_roce_hw_v2.h

+12 −0
Original line number Diff line number Diff line
@@ -288,6 +288,10 @@ struct hns_roce_v2_cq_context { 
	__le32 byte_64_se_cqe_idx;

};



#define CQC_CQE_BA_L_S 3

#define CQC_CQE_BA_H_S (32 + CQC_CQE_BA_L_S)

#define CQC_CQE_DB_RECORD_ADDR_H_S 32



#define HNS_ROCE_V2_CQ_DEFAULT_BURST_NUM 0x0

#define HNS_ROCE_V2_CQ_DEFAULT_INTERVAL	0x0
@@ -482,6 +486,11 @@ struct hns_roce_v2_qp_context { 


	struct hns_roce_v2_qp_context_ex ext;

};

#define QPC_TRRL_BA_L_S 4

#define QPC_TRRL_BA_M_S (16 + QPC_TRRL_BA_L_S)

#define QPC_TRRL_BA_H_S (32 + QPC_TRRL_BA_M_S)

#define QPC_IRRL_BA_L_S 6

#define QPC_IRRL_BA_H_S (32 + QPC_IRRL_BA_L_S)



#define QPC_FIELD_LOC(h, l) FIELD_LOC(struct hns_roce_v2_qp_context, h, l)
@@ -752,6 +761,9 @@ struct hns_roce_v2_mpt_entry { 
	__le32	byte_64_buf_pa1;

};



#define MPT_PBL_BUF_ADDR_S 6

#define MPT_PBL_BA_ADDR_S 3



#define MPT_FIELD_LOC(h, l) FIELD_LOC(struct hns_roce_v2_mpt_entry, h, l)



#define MPT_ST MPT_FIELD_LOC(1, 0)

drivers/infiniband/hw/hns/hns_roce_qp.c

+2 −1
Original line number Diff line number Diff line
@@ -416,7 +416,8 @@ static void free_qpn(struct hns_roce_dev *hr_dev, struct hns_roce_qp *hr_qp) 


	bankid = get_qp_bankid(hr_qp->qpn);



	ida_free(&hr_dev->qp_table.bank[bankid].ida, hr_qp->qpn >> 3);

	ida_free(&hr_dev->qp_table.bank[bankid].ida,

		 hr_qp->qpn / HNS_ROCE_QP_BANK_NUM);



	mutex_lock(&hr_dev->qp_table.bank_mutex);

	hr_dev->qp_table.bank[bankid].inuse--;