Commit 97c78d0a authored by Jakub Kicinski's avatar Jakub Kicinski
Browse files

Merge git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net 



drivers/net/wwan/mhi_wwan_mbim.c - drop the extra arg.

Signed-off-by: default avatarJakub Kicinski <kuba@kernel.org>
parents deecae7d 73367f05

Documentation/devicetree/bindings/riscv/sifive-l2-cache.yaml

+4 −4
Original line number Diff line number Diff line
@@ -24,8 +24,8 @@ allOf: 
select:

  properties:

    compatible:

      items:

        - enum:

      contains:

        enum:

          - sifive,fu540-c000-ccache

          - sifive,fu740-c000-ccache

MAINTAINERS

+19 −2
Original line number Diff line number Diff line
@@ -3866,6 +3866,16 @@ L: bcm-kernel-feedback-list@broadcom.com 
S:	Maintained

F:	drivers/mtd/nand/raw/brcmnand/









BROADCOM STB PCIE DRIVER









M:	Jim Quinlan <jim2101024@gmail.com>









M:	Nicolas Saenz Julienne <nsaenz@kernel.org>









M:	Florian Fainelli <f.fainelli@gmail.com>









M:	bcm-kernel-feedback-list@broadcom.com









L:	linux-pci@vger.kernel.org









S:	Maintained









F:	Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml









F:	drivers/pci/controller/pcie-brcmstb.c

















BROADCOM SYSTEMPORT ETHERNET DRIVER









M:	Florian Fainelli <f.fainelli@gmail.com>









L:	bcm-kernel-feedback-list@broadcom.com








@@ -4498,7 +4508,7 @@ L:	clang-built-linux@googlegroups.com







S:	Supported









W:	https://clangbuiltlinux.github.io/









B:	https://github.com/ClangBuiltLinux/linux/issues









C:	irc://chat.freenode.net/clangbuiltlinux









C:	irc://irc.libera.chat/clangbuiltlinux









F:	Documentation/kbuild/llvm.rst









F:	include/linux/compiler-clang.h









F:	scripts/clang-tools/








@@ -6952,7 +6962,7 @@ F:	include/uapi/linux/mdio.h







F:	include/uapi/linux/mii.h

















EXFAT FILE SYSTEM









M:	Namjae Jeon <namjae.jeon@samsung.com>









M:	Namjae Jeon <linkinjeon@kernel.org>









M:	Sungjong Seo <sj1557.seo@samsung.com>









L:	linux-fsdevel@vger.kernel.org









S:	Maintained








@@ -14457,6 +14467,13 @@ S:	Maintained







F:	Documentation/devicetree/bindings/pci/hisilicon-histb-pcie.txt









F:	drivers/pci/controller/dwc/pcie-histb.c

















PCIE DRIVER FOR INTEL LGM GW SOC









M:	Rahul Tanwar <rtanwar@maxlinear.com>









L:	linux-pci@vger.kernel.org









S:	Maintained









F:	Documentation/devicetree/bindings/pci/intel-gw-pcie.yaml









F:	drivers/pci/controller/dwc/pcie-intel-gw.c

















PCIE DRIVER FOR MEDIATEK









M:	Ryder Lee <ryder.lee@mediatek.com>









M:	Jianjun Wang <jianjun.wang@mediatek.com>
































Makefile



+1
−1






























Original line number
Diff line number
Diff line







@@ -2,7 +2,7 @@







VERSION = 5









PATCHLEVEL = 14









SUBLEVEL = 0









EXTRAVERSION = -rc6









EXTRAVERSION = -rc7









NAME = Opossums on Parade



















# *DOCUMENTATION*
































arch/arm/configs/nhk8815_defconfig



+3
−5






























Original line number
Diff line number
Diff line







@@ -15,8 +15,6 @@ CONFIG_SLAB=y







CONFIG_ARCH_NOMADIK=y









CONFIG_MACH_NOMADIK_8815NHK=y









CONFIG_AEABI=y









CONFIG_ZBOOT_ROM_TEXT=0x0









CONFIG_ZBOOT_ROM_BSS=0x0









CONFIG_MODULES=y









CONFIG_MODULE_UNLOAD=y









# CONFIG_BLK_DEV_BSG is not set








@@ -52,9 +50,9 @@ CONFIG_MTD_BLOCK=y







CONFIG_MTD_ONENAND=y









CONFIG_MTD_ONENAND_VERIFY_WRITE=y









CONFIG_MTD_ONENAND_GENERIC=y









CONFIG_MTD_NAND_ECC_SW_HAMMING_SMC=y









CONFIG_MTD_RAW_NAND=y









CONFIG_MTD_NAND_FSMC=y









CONFIG_MTD_NAND_ECC_SW_HAMMING_SMC=y









CONFIG_BLK_DEV_LOOP=y









CONFIG_BLK_DEV_CRYPTOLOOP=y









CONFIG_BLK_DEV_RAM=y








@@ -97,6 +95,7 @@ CONFIG_REGULATOR=y







CONFIG_DRM=y









CONFIG_DRM_PANEL_TPO_TPG110=y









CONFIG_DRM_PL111=y









CONFIG_FB=y









CONFIG_BACKLIGHT_CLASS_DEVICE=y









CONFIG_BACKLIGHT_PWM=y









CONFIG_FRAMEBUFFER_CONSOLE=y








@@ -136,9 +135,8 @@ CONFIG_NLS_ISO8859_15=y







CONFIG_CRYPTO_MD5=y









CONFIG_CRYPTO_SHA1=y









CONFIG_CRYPTO_DES=y









# CONFIG_DEBUG_BUGVERBOSE is not set









CONFIG_DEBUG_INFO=y









# CONFIG_ENABLE_MUST_CHECK is not set









CONFIG_DEBUG_FS=y









# CONFIG_SCHED_DEBUG is not set









# CONFIG_DEBUG_PREEMPT is not set








# CONFIG_DEBUG_BUGVERBOSE is not set
























arch/arm/mach-ixp4xx/include/mach/ixp4xx-regs.h



+24
−24






























Original line number
Diff line number
Diff line







@@ -218,30 +218,30 @@







/*









 * PCI Control/Status Registers









 */









#define IXP4XX_PCI_CSR(x) ((volatile u32 *)(IXP4XX_PCI_CFG_BASE_VIRT+(x)))



















#define PCI_NP_AD               IXP4XX_PCI_CSR(PCI_NP_AD_OFFSET)









#define PCI_NP_CBE              IXP4XX_PCI_CSR(PCI_NP_CBE_OFFSET)









#define PCI_NP_WDATA            IXP4XX_PCI_CSR(PCI_NP_WDATA_OFFSET)









#define PCI_NP_RDATA            IXP4XX_PCI_CSR(PCI_NP_RDATA_OFFSET)









#define PCI_CRP_AD_CBE          IXP4XX_PCI_CSR(PCI_CRP_AD_CBE_OFFSET)









#define PCI_CRP_WDATA           IXP4XX_PCI_CSR(PCI_CRP_WDATA_OFFSET)









#define PCI_CRP_RDATA           IXP4XX_PCI_CSR(PCI_CRP_RDATA_OFFSET)









#define PCI_CSR                 IXP4XX_PCI_CSR(PCI_CSR_OFFSET) 









#define PCI_ISR                 IXP4XX_PCI_CSR(PCI_ISR_OFFSET)









#define PCI_INTEN               IXP4XX_PCI_CSR(PCI_INTEN_OFFSET)









#define PCI_DMACTRL             IXP4XX_PCI_CSR(PCI_DMACTRL_OFFSET)









#define PCI_AHBMEMBASE          IXP4XX_PCI_CSR(PCI_AHBMEMBASE_OFFSET)









#define PCI_AHBIOBASE           IXP4XX_PCI_CSR(PCI_AHBIOBASE_OFFSET)









#define PCI_PCIMEMBASE          IXP4XX_PCI_CSR(PCI_PCIMEMBASE_OFFSET)









#define PCI_AHBDOORBELL         IXP4XX_PCI_CSR(PCI_AHBDOORBELL_OFFSET)









#define PCI_PCIDOORBELL         IXP4XX_PCI_CSR(PCI_PCIDOORBELL_OFFSET)









#define PCI_ATPDMA0_AHBADDR     IXP4XX_PCI_CSR(PCI_ATPDMA0_AHBADDR_OFFSET)









#define PCI_ATPDMA0_PCIADDR     IXP4XX_PCI_CSR(PCI_ATPDMA0_PCIADDR_OFFSET)









#define PCI_ATPDMA0_LENADDR     IXP4XX_PCI_CSR(PCI_ATPDMA0_LENADDR_OFFSET)









#define PCI_ATPDMA1_AHBADDR     IXP4XX_PCI_CSR(PCI_ATPDMA1_AHBADDR_OFFSET)









#define PCI_ATPDMA1_PCIADDR     IXP4XX_PCI_CSR(PCI_ATPDMA1_PCIADDR_OFFSET)









#define PCI_ATPDMA1_LENADDR     IXP4XX_PCI_CSR(PCI_ATPDMA1_LENADDR_OFFSET)









#define _IXP4XX_PCI_CSR(x) ((volatile u32 *)(IXP4XX_PCI_CFG_BASE_VIRT+(x)))



















#define PCI_NP_AD               _IXP4XX_PCI_CSR(PCI_NP_AD_OFFSET)









#define PCI_NP_CBE              _IXP4XX_PCI_CSR(PCI_NP_CBE_OFFSET)









#define PCI_NP_WDATA            _IXP4XX_PCI_CSR(PCI_NP_WDATA_OFFSET)









#define PCI_NP_RDATA            _IXP4XX_PCI_CSR(PCI_NP_RDATA_OFFSET)









#define PCI_CRP_AD_CBE          _IXP4XX_PCI_CSR(PCI_CRP_AD_CBE_OFFSET)









#define PCI_CRP_WDATA           _IXP4XX_PCI_CSR(PCI_CRP_WDATA_OFFSET)









#define PCI_CRP_RDATA           _IXP4XX_PCI_CSR(PCI_CRP_RDATA_OFFSET)









#define PCI_CSR                 _IXP4XX_PCI_CSR(PCI_CSR_OFFSET) 









#define PCI_ISR                 _IXP4XX_PCI_CSR(PCI_ISR_OFFSET)









#define PCI_INTEN               _IXP4XX_PCI_CSR(PCI_INTEN_OFFSET)









#define PCI_DMACTRL             _IXP4XX_PCI_CSR(PCI_DMACTRL_OFFSET)









#define PCI_AHBMEMBASE          _IXP4XX_PCI_CSR(PCI_AHBMEMBASE_OFFSET)









#define PCI_AHBIOBASE           _IXP4XX_PCI_CSR(PCI_AHBIOBASE_OFFSET)









#define PCI_PCIMEMBASE          _IXP4XX_PCI_CSR(PCI_PCIMEMBASE_OFFSET)









#define PCI_AHBDOORBELL         _IXP4XX_PCI_CSR(PCI_AHBDOORBELL_OFFSET)









#define PCI_PCIDOORBELL         _IXP4XX_PCI_CSR(PCI_PCIDOORBELL_OFFSET)









#define PCI_ATPDMA0_AHBADDR     _IXP4XX_PCI_CSR(PCI_ATPDMA0_AHBADDR_OFFSET)









#define PCI_ATPDMA0_PCIADDR     _IXP4XX_PCI_CSR(PCI_ATPDMA0_PCIADDR_OFFSET)









#define PCI_ATPDMA0_LENADDR     _IXP4XX_PCI_CSR(PCI_ATPDMA0_LENADDR_OFFSET)









#define PCI_ATPDMA1_AHBADDR     _IXP4XX_PCI_CSR(PCI_ATPDMA1_AHBADDR_OFFSET)









#define PCI_ATPDMA1_PCIADDR     _IXP4XX_PCI_CSR(PCI_ATPDMA1_PCIADDR_OFFSET)









#define PCI_ATPDMA1_LENADDR     _IXP4XX_PCI_CSR(PCI_ATPDMA1_LENADDR_OFFSET)



















/*









 * PCI register values and bit definitions