Commit 97a9b60f authored by shiwu.zhang's avatar shiwu.zhang Committed by Alex Deucher
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drm/amdgpu: update gc golden register for arcturus 



Update golden setting to improve performance on HPC
and ML apps

Signed-off-by: default avatarshiwu.zhang <shiwu.zhang@amd.com>
Tested-by: default avatargang.long <gang.long@amd.com>
Reviewed-by: default avatarguchun.chen <guchun.chen@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 2c5b8080

drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c

+1 −0
Original line number Original line Diff line number Diff line
@@ -691,6 +691,7 @@ static const struct soc15_reg_golden golden_settings_gc_9_4_1_arct[] = 
	SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_5_ARCT, 0x3ff, 0x135),

	SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_5_ARCT, 0x3ff, 0x135),

	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_CONFIG, 0xffffffff, 0x011A0000),

	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_CONFIG, 0xffffffff, 0x011A0000),

	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_FIFO_SIZES, 0xffffffff, 0x00000f00),

	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_FIFO_SIZES, 0xffffffff, 0x00000f00),

	SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_UTCL1_CNTL1, 0x30000000, 0x30000000)

};

};





static const struct soc15_reg_rlcg rlcg_access_gc_9_0[] = {

static const struct soc15_reg_rlcg rlcg_access_gc_9_0[] = {