Commit 97a71c44 authored by Sean Christopherson's avatar Sean Christopherson Committed by Paolo Bonzini
Browse files

KVM: x86: Purge "highest ISR" cache when updating APICv state 



Purge the "highest ISR" cache when updating APICv state on a vCPU.  The
cache must not be used when APICv is active as hardware may emulate EOIs
(and other operations) without exiting to KVM.

This fixes a bug where KVM will effectively block IRQs in perpetuity due
to the "highest ISR" never getting reset if APICv is activated on a vCPU
while an IRQ is in-service.  Hardware emulates the EOI and KVM never gets
a chance to update its cache.

Fixes: b26a695a ("kvm: lapic: Introduce APICv update helper function")
Cc: stable@vger.kernel.org
Cc: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com>
Cc: Maxim Levitsky <mlevitsk@redhat.com>
Reviewed-by: default avatarPaolo Bonzini <pbonzini@redhat.com>
Reviewed-by: default avatarMaxim Levitsky <mlevitsk@redhat.com>
Signed-off-by: default avatarSean Christopherson <seanjc@google.com>
Message-Id: <20230106011306.85230-3-seanjc@google.com>
Signed-off-by: default avatarPaolo Bonzini <pbonzini@redhat.com>
parent 0a19807b

arch/x86/kvm/lapic.c

+1 −2
Original line number Diff line number Diff line
@@ -2424,6 +2424,7 @@ void kvm_apic_update_apicv(struct kvm_vcpu *vcpu) 
		 */

		apic->isr_count = count_vectors(apic->regs + APIC_ISR);

	}

	apic->highest_isr_cache = -1;

}



void kvm_lapic_reset(struct kvm_vcpu *vcpu, bool init_event)
@@ -2479,7 +2480,6 @@ void kvm_lapic_reset(struct kvm_vcpu *vcpu, bool init_event) 
		kvm_lapic_set_reg(apic, APIC_TMR + 0x10 * i, 0);

	}

	kvm_apic_update_apicv(vcpu);

	apic->highest_isr_cache = -1;

	update_divide_count(apic);

	atomic_set(&apic->lapic_timer.pending, 0);
@@ -2767,7 +2767,6 @@ int kvm_apic_set_state(struct kvm_vcpu *vcpu, struct kvm_lapic_state *s) 
	__start_apic_timer(apic, APIC_TMCCT);

	kvm_lapic_set_reg(apic, APIC_TMCCT, 0);

	kvm_apic_update_apicv(vcpu);

	apic->highest_isr_cache = -1;

	if (apic->apicv_active) {

		static_call_cond(kvm_x86_apicv_post_state_restore)(vcpu);

		static_call_cond(kvm_x86_hwapic_irr_update)(vcpu, apic_find_highest_irr(apic));