Commit 9757300d authored by Ninad Naik's avatar Ninad Naik Committed by Linus Walleij
Browse files

pinctrl: qcom: Add intr_target_width field to support increased number of interrupt targets 



SA8775 and newer target have added support for an increased number of
interrupt targets. To implement this change, the intr_target field, which
is used to configure the interrupt target in the interrupt configuration
register is increased from 3 bits to 4 bits.

In accordance to these updates, a new intr_target_width member is
introduced in msm_pingroup structure. This member stores the value of
width of intr_target field in the interrupt configuration register. This
value is used to dynamically calculate and generate mask for setting the
intr_target field. By default, this mask is set to 3 bit wide, to ensure
backward compatibility with the older targets.

Fixes: 4b6b1855 ("pinctrl: qcom: add the tlmm driver sa8775p platforms")
Tested-by: Andrew Halaney <ahalaney@redhat.com> # sa8775p-ride
Signed-off-by: default avatarNinad Naik <quic_ninanaik@quicinc.com>
Reviewed-by: default avatarKonrad Dybcio <konrad.dybcio@linaro.org>
Reviewed-by: default avatarBjorn Andersson <quic_bjorande@quicinc.com>
Link: https://lore.kernel.org/r/20230809100634.3961-1-quic_ninanaik@quicinc.com


Signed-off-by: default avatarLinus Walleij <linus.walleij@linaro.org>
parent f00295e8

drivers/pinctrl/qcom/pinctrl-msm.c

+6 −3
Original line number Diff line number Diff line
@@ -1038,6 +1038,7 @@ static int msm_gpio_irq_set_type(struct irq_data *d, unsigned int type) 
	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);

	struct msm_pinctrl *pctrl = gpiochip_get_data(gc);

	const struct msm_pingroup *g;

	u32 intr_target_mask = GENMASK(2, 0);

	unsigned long flags;

	bool was_enabled;

	u32 val;
@@ -1074,13 +1075,15 @@ static int msm_gpio_irq_set_type(struct irq_data *d, unsigned int type) 
	 * With intr_target_use_scm interrupts are routed to

	 * application cpu using scm calls.

	 */

	if (g->intr_target_width)

		intr_target_mask = GENMASK(g->intr_target_width - 1, 0);



	if (pctrl->intr_target_use_scm) {

		u32 addr = pctrl->phys_base[0] + g->intr_target_reg;

		int ret;



		qcom_scm_io_readl(addr, &val);



		val &= ~(7 << g->intr_target_bit);

		val &= ~(intr_target_mask << g->intr_target_bit);

		val |= g->intr_target_kpss_val << g->intr_target_bit;



		ret = qcom_scm_io_writel(addr, val);
@@ -1090,7 +1093,7 @@ static int msm_gpio_irq_set_type(struct irq_data *d, unsigned int type) 
				d->hwirq);

	} else {

		val = msm_readl_intr_target(pctrl, g);

		val &= ~(7 << g->intr_target_bit);

		val &= ~(intr_target_mask << g->intr_target_bit);

		val |= g->intr_target_kpss_val << g->intr_target_bit;

		msm_writel_intr_target(val, pctrl, g);

	}

drivers/pinctrl/qcom/pinctrl-msm.h

+2 −0
Original line number Diff line number Diff line
@@ -59,6 +59,7 @@ struct pinctrl_pin_desc; 
 * @intr_status_bit:      Offset in @intr_status_reg for reading and acking the interrupt

 *                        status.

 * @intr_target_bit:      Offset in @intr_target_reg for configuring the interrupt routing.

 * @intr_target_width:    Number of bits used for specifying interrupt routing target.

 * @intr_target_kpss_val: Value in @intr_target_bit for specifying that the interrupt from

 *                        this gpio should get routed to the KPSS processor.

 * @intr_raw_status_bit:  Offset in @intr_cfg_reg for the raw status bit.
@@ -100,6 +101,7 @@ struct msm_pingroup { 
	unsigned intr_ack_high:1;



	unsigned intr_target_bit:5;

	unsigned intr_target_width:5;

	unsigned intr_target_kpss_val:5;

	unsigned intr_raw_status_bit:5;

	unsigned intr_polarity_bit:5;

drivers/pinctrl/qcom/pinctrl-sa8775p.c

+1 −0
Original line number Diff line number Diff line
@@ -46,6 +46,7 @@ 
		.intr_enable_bit = 0,		\

		.intr_status_bit = 0,		\

		.intr_target_bit = 5,		\

		.intr_target_width = 4,		\

		.intr_target_kpss_val = 3,	\

		.intr_raw_status_bit = 4,	\

		.intr_polarity_bit = 1,		\