Commit 9730870b authored by Huacai Chen's avatar Huacai Chen
Browse files

LoongArch: Fix hw_breakpoint_control() for watchpoints 



In hw_breakpoint_control(), encode_ctrl_reg() has already encoded the
MWPnCFG3_LoadEn/MWPnCFG3_StoreEn bits in info->ctrl. We don't need to
add (1 << MWPnCFG3_LoadEn | 1 << MWPnCFG3_StoreEn) unconditionally.

Otherwise we can't set read watchpoint and write watchpoint separately.

Cc: stable@vger.kernel.org
Signed-off-by: default avatarHuacai Chen <chenhuacai@loongson.cn>
parent 656f9aec

arch/loongarch/kernel/hw_breakpoint.c

+1 −2
Original line number Diff line number Diff line
@@ -207,8 +207,7 @@ static int hw_breakpoint_control(struct perf_event *bp, 
			write_wb_reg(CSR_CFG_CTRL, i, 0, CTRL_PLV_ENABLE);

		} else {

			ctrl = encode_ctrl_reg(info->ctrl);

			write_wb_reg(CSR_CFG_CTRL, i, 1, ctrl | CTRL_PLV_ENABLE |

				     1 << MWPnCFG3_LoadEn | 1 << MWPnCFG3_StoreEn);

			write_wb_reg(CSR_CFG_CTRL, i, 1, ctrl | CTRL_PLV_ENABLE);

		}

		enable = csr_read64(LOONGARCH_CSR_CRMD);

		csr_write64(CSR_CRMD_WE | enable, LOONGARCH_CSR_CRMD);