Commit 9724bb66 authored by Tao Zhou's avatar Tao Zhou Committed by Alex Deucher
Browse files

drm/amdgpu: add cyan_skillfish support in gfx v10 



Add gfx support for cyan_skillfish.

Signed-off-by: default avatarTao Zhou <tao.zhou1@amd.com>
Reviewed-by: default avatarHawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 9dbd8a12

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

+14 −0
Original line number Diff line number Diff line
@@ -3545,6 +3545,8 @@ static const struct soc15_reg_golden golden_settings_gc_10_3_5[] = { 
	 (SH_MEM_RETRY_MODE_ALL << SH_MEM_CONFIG__RETRY_MODE__SHIFT) | \

	 (3 << SH_MEM_CONFIG__INITIAL_INST_PREFETCH__SHIFT))



/* TODO: pending on golden setting value of gb address config */

#define CYAN_SKILLFISH_GB_ADDR_CONFIG_GOLDEN 0x00100044



static void gfx_v10_0_set_ring_funcs(struct amdgpu_device *adev);

static void gfx_v10_0_set_irq_funcs(struct amdgpu_device *adev);
@@ -3942,6 +3944,7 @@ static void gfx_v10_0_check_fw_write_wait(struct amdgpu_device *adev) 
	case CHIP_NAVI10:

	case CHIP_NAVI12:

	case CHIP_NAVI14:

	case CHIP_CYAN_SKILLFISH:

		if ((adev->gfx.me_fw_version >= 0x00000046) &&

		    (adev->gfx.me_feature_version >= 27) &&

		    (adev->gfx.pfp_fw_version >= 0x00000068) &&
@@ -4661,6 +4664,14 @@ static void gfx_v10_0_gpu_early_init(struct amdgpu_device *adev) 
		adev->gfx.config.gb_addr_config_fields.num_pkrs =

			1 << REG_GET_FIELD(gb_addr_config, GB_ADDR_CONFIG, NUM_PKRS);

		break;

	case CHIP_CYAN_SKILLFISH:

		adev->gfx.config.max_hw_contexts = 8;

		adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;

		adev->gfx.config.sc_prim_fifo_size_backend = 0x100;

		adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;

		adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0;

		gb_addr_config = CYAN_SKILLFISH_GB_ADDR_CONFIG_GOLDEN;

		break;

	default:

		BUG();

		break;
@@ -4765,6 +4776,7 @@ static int gfx_v10_0_sw_init(void *handle) 
	case CHIP_NAVI10:

	case CHIP_NAVI14:

	case CHIP_NAVI12:

	case CHIP_CYAN_SKILLFISH:

		adev->gfx.me.num_me = 1;

		adev->gfx.me.num_pipe_per_me = 1;

		adev->gfx.me.num_queue_per_pipe = 1;
@@ -7729,6 +7741,7 @@ static int gfx_v10_0_early_init(void *handle) 
	case CHIP_NAVI10:

	case CHIP_NAVI14:

	case CHIP_NAVI12:

	case CHIP_CYAN_SKILLFISH:

		adev->gfx.num_gfx_rings = GFX10_NUM_GFX_RINGS_NV1X;

		break;

	case CHIP_SIENNA_CICHLID:
@@ -9489,6 +9502,7 @@ static void gfx_v10_0_set_rlc_funcs(struct amdgpu_device *adev) 
	case CHIP_DIMGREY_CAVEFISH:

	case CHIP_BEIGE_GOBY:

	case CHIP_YELLOW_CARP:

	case CHIP_CYAN_SKILLFISH:

		adev->gfx.rlc.funcs = &gfx_v10_0_rlc_funcs;

		break;

	case CHIP_NAVI12: