Commit 972243f9 authored by Vladimir Stempen's avatar Vladimir Stempen Committed by Alex Deucher
Browse files

drm/amd/display: fix FCLK pstate change underflow 



[Why]
Currently we set FCLK p-state change
watermark calculated based on dummy
p-state latency when UCLK p-state is
not supported

[How]
Calculate FCLK p-state change watermark
based on on FCLK pstate change latency
in case UCLK p-state is not supported

Reviewed-by: default avatarNevenko Stupar <Nevenko.Stupar@amd.com>
Acked-by: default avatarAlex Hung <alex.hung@amd.com>
Signed-off-by: default avatarVladimir Stempen <vladimir.stempen@amd.com>
Tested-by: default avatarDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 32e3da43

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

+4 −0
Original line number Diff line number Diff line
@@ -2126,6 +2126,10 @@ void dcn32_calculate_wm_and_dlg_fpu(struct dc *dc, struct dc_state *context, 
		 */

		context->bw_ctx.bw.dcn.watermarks.a = context->bw_ctx.bw.dcn.watermarks.c;

		context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.pstate_change_ns = 0;

		/* Calculate FCLK p-state change watermark based on FCLK pstate change latency in case

		 * UCLK p-state is not supported, to avoid underflow in case FCLK pstate is supported

		 */

		context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.fclk_pstate_change_ns = get_fclk_watermark(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;

	} else {

		/* Set A:

		 * All clocks min.